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21. 发明授权

US06475817B2 Method of fabricating integrated circuits, providing improved so-called saw bows 失效
标题翻译：制造集成电路的方法，提供改进的所谓的锯弓
公开(公告)号：US06475817B2
公开(公告)日：2002-11-05
申请号：US09908559
申请日：2001-07-19
申请人： Ewald Bergler , Josef Preishuber-Pfluegl , Reinhard Fetzer , Haiko Klepzig
发明人： Ewald Bergler , Josef Preishuber-Pfluegl , Reinhard Fetzer , Haiko Klepzig
IPC分类号： H01L2166
CPC分类号： H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (6) has a semiconductor die (47) and an integrated circuit configuration (16) realized on the semiconductor die (47) and situated within bounding faces (52, 53, 54, 55) of the semiconductor die (47), in which two conductor track sections (34, 35) have been provided, which issue from the integrated circuit configuration (16) and which each extend up to a bounding face (55) and which are required for the application of a useful signal (BR1) utilized for test purposes during the fabrication of the integrated circuit (6), and in which an additional conductor track section (41) has been provided, which is disposed adjacent the two conductor track sections (34, 35) and which issues from the integrated circuit configuration (16) and extends toward a bounding surface (55) and preferably up to this bounding face (55) and which serves for the application of a spurious signal (BR2) which interferes with testing.
摘要翻译：集成电路（6）具有在半导体管芯（47）上实现并位于半导体管芯（47）的边界面（52,53,54,55）内的半导体管芯（47）和集成电路结构（16），其中已经提供了两个导体轨道部分（34,35），其从集成电路配置（16）发出并且各自延伸到边界面（55），并且是施加有用信号所必需的 BR1）用于在集成电路（6）的制造期间用于测试目的，并且其中已经设置了附加的导体轨道部分（41），其布置成与两个导体轨道部分（34,35）相邻并且从集成电路配置（16）并且朝向边界表面（55）延伸，并且优选地直到该边界面（55），并且用于施加干扰测试的寄生信号（BR2）。

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