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21. 发明授权

US08569820B2 Capacitor having a plurality of parallel conductive members 有权
标题翻译：具有多个平行导电构件的电容器
公开(公告)号：US08569820B2
公开(公告)日：2013-10-29
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

22. 发明授权

US07767562B2 Method of implanting using a shadow effect 有权
标题翻译：使用阴影效果进行植入的方法
公开(公告)号：US07767562B2
公开(公告)日：2010-08-03
申请号：US11235330
申请日：2005-09-26
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L21/425
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要翻译：半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

23. 发明申请

US20090160020A1 Moisture Barrier Capacitors in Semiconductor Components 有权
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20090160020A1
公开(公告)日：2009-06-25
申请号：US11962395
申请日：2007-12-21
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L29/92 , H01L21/02 , H01L21/66
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

24. 发明申请

US20120099243A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120099243A1
公开(公告)日：2012-04-26
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01G4/005
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

25. 发明授权

US06544855B1 Process flow for sacrificial collar with polysilicon void 有权
标题翻译：具有多晶硅空隙的牺牲环的工艺流程
公开(公告)号：US06544855B1
公开(公告)日：2003-04-08
申请号：US10041779
申请日：2001-10-19
申请人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
发明人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within the trenches (114). A semiconductor material layer (120) is deposited over the nitride layer (116) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug (132) is formed at the top surface of the recessed semiconductor material layer (120), leaving a void (133) in the bottom of each trench (114). An oxide layer (134) and nitride layer (136) are formed over the wafer (100) and trenches (116), and the semiconductor material plug (132) and semiconductor material layer (120) are removed from the bottom of the trenches (116).
摘要翻译：一种用于在半导体晶片（100）的深沟槽（114）的顶部上形成牺牲套环的工艺。氮化物层（116）沉积在沟槽（114）内。半导体材料层（120）沉积在氮化物层（116）上并且被回蚀刻到衬底112顶表面下方的预定高度（A）。半导体材料插塞（132）形成在凹陷半导体材料层（120）的顶表面处，在每个沟槽（114）的底部留下空隙（133）。在晶片（100）和沟槽（116）之上形成氧化物层（134）和氮化物层（136），半导体材料插塞（132）和半导体材料层（120）从沟槽的底部 116）。

26. 发明授权

US06358867B1 Orientation independent oxidation of silicon 有权
标题翻译：硅取向独立氧化
公开(公告)号：US06358867B1
公开(公告)日：2002-03-19
申请号：US09596097
申请日：2000-06-16
申请人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
发明人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C30B29/06 , C30B33/00 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28176 , H01L21/28211 , H01L21/31662 , H01L21/76202 , H01L29/513 , H01L29/518 , Y10S438/973
摘要： A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.
摘要翻译：根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中硅表面具有硅晶体的至少两个不同晶体取向的衬底。形成氧化表面的原子氧（O）。通过使原子氧与表面反应，在表面上形成氧化物，同时形成表面上氧化物的基本均匀的厚度。

27. 发明授权

US06309924B1 Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
标题翻译： DRAM单元形成自限多晶硅LOCOS的方法
公开(公告)号：US06309924B1
公开(公告)日：2001-10-30
申请号：US09585898
申请日：2000-06-02
申请人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
发明人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
摘要翻译：一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。首先在硅衬底中形成DRAM沟槽。然后，氮化物衬垫沉积在硅沟槽壁上。氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。然后将一层非晶硅沉积在氮化物衬垫上。在非晶硅的氧化表面上沉积氮化硅层。在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

28. 发明授权

US06235651B1 Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication 有权
标题翻译：用于改善半导体晶片制造中的薄层的厚度均匀性的方法
公开(公告)号：US06235651B1
公开(公告)日：2001-05-22
申请号：US09395952
申请日：1999-09-14
申请人： Martin Schrems , Helmut Horst Tews
发明人： Martin Schrems , Helmut Horst Tews
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662
摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.
摘要翻译：提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度从炉中回收含氧化物层的晶片。

29. 发明授权

US08003470B2 Strained semiconductor device and method of making the same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US08003470B2
公开(公告)日：2011-08-23
申请号：US11224825
申请日：2005-09-13
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

30. 发明申请

US20090141424A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090141424A1
公开(公告)日：2009-06-04
申请号：US11947591
申请日：2007-11-29
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01G4/33 , H01G4/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

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