专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20060057815A1 Method of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060057815A1
公开(公告)日：2006-03-16
申请号：US11212237
申请日：2005-08-26
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , G03F9/708 , G03F9/7084 , H01L21/76237 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a high-voltage semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer is patterned to form a stepped portion of the mask layer. A photoresist pattern for defining an active region of the substrate is formed on the substrate using the stepped portion as an alignment mark. The alignment mark for aligning the photoresist pattern that is used for the active region of the high-voltage semiconductor device may be formed by reduced processing steps with reduced incidence of contamination, thereby improving device performance with higher productivity and reduced production costs.
摘要翻译：在制造高电压半导体器件的方法中，在半导体衬底上形成掩模层。图案化掩模层以形成掩模层的阶梯部分。使用阶梯部作为对准标记，在基板上形成用于限定基板的有源区域的光致抗蚀剂图案。用于对准用于高电压半导体器件的有源区域的光致抗蚀剂图案的对准标记可以通过减少的污染发生率的减少的处理步骤形成，从而以更高的生产率和降低的生产成本提高器件性能。

22. 发明授权

US08143677B2 Transistor, a transistor arrangement and method thereof 有权
标题翻译：晶体管，晶体管结构及其方法
公开(公告)号：US08143677B2
公开(公告)日：2012-03-27
申请号：US12659107
申请日：2010-02-25
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
摘要翻译：提供一种晶体管，晶体管结构及其方法。示例性方法可以包括确定晶体管的栅极宽度是否已被调整; 以及如果所述确定步骤确定所述晶体管的栅极宽度，则基于所述调整的栅极宽度来调整所述晶体管的高浓度杂质掺杂区域和所述晶体管的器件隔离层之间的距离。示例性晶体管可以包括限定第一有源区的第一器件隔离层，具有第一栅极宽度并与第一有源区交叉的第一栅极线，首先在第一有源区中形成的第一低浓度杂质掺杂区和第一栅极线的第二面和形成在低浓度杂质掺杂区域中的第一较高浓度杂质掺杂区，并且不与栅极线和器件隔离层接触。

23. 发明申请

US20060278920A1 Metal oxide semiconductor field-effect transistor (MOSFET) and method of fabricating the same 审中-公开
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）及其制造方法
公开(公告)号：US20060278920A1
公开(公告)日：2006-12-14
申请号：US11443385
申请日：2006-05-30
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823456
摘要： A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within the active region, and a gate electrode formed on the active region between the source region and the drain region. Furthermore, the MOSFET also includes a gate insulating layer formed between the active region and the gate electrode. The gate insulating layer includes a central gate insulating layer disposed under central portion of the gate electrode, an edge gate insulating layer disposed under an edge portion of the gate electrode to have a bottom surface level with a bottom of the central gate insulating layer and an upper surface protruding to be higher than an upper surface of the central gate insulating layer.
摘要翻译：提供金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET包括半导体衬底，设置在半导体衬底的预定部分上以限定有源区域的器件隔离区域，围绕有源区域内的沟道区域彼此间隔开的源极区域和漏极区域，以及栅极在源极区域和漏极区域之间的有源区域上形成电极。此外，MOSFET还包括在有源区和栅电极之间形成的栅极绝缘层。所述栅极绝缘层包括设置在所述栅极电极的中心部分的中心栅极绝缘层，设置在所述栅极电极的边缘部分下方的边缘栅极绝缘层，以具有与所述中心栅极绝缘层的底部的底面水平面，上表面突出高于中心栅极绝缘层的上表面。

24. 发明申请

US20060234435A1 Semiconductor device having one-time programmable ROM and method of fabricating the same 失效
公开(公告)号：US20060234435A1
公开(公告)日：2006-10-19
申请号：US11448200
申请日：2006-06-07
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/11531 , H01L29/66825
摘要： A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The OTP ROM capacitor has a lower electrode, an upper intermetal dielectric, and an upper electrode which are stacked in the order named. The OTP ROM capacitor is disposed on the MOS transistor, and the floating gate electrode and the lower electrode are connected by a floating gate plug to constitute an electrically insulated conductive structure. The upper intermetal dielectric is made of at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride and may be disposed on an entire surface of the semiconductor substrate. A capacitor formed together with the OTP ROM is disposed at the peripheral circuit region.

25. 发明授权

US06727568B2 Semiconductor device having a shallow trench isolation and method of fabricating the same 有权
公开(公告)号：US06727568B2
公开(公告)日：2004-04-27
申请号：US10105544
申请日：2002-03-25
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L2900
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28167 , H01L21/28211 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L29/42368 , H01L29/513 , H01L29/7835
摘要： The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

26. 发明授权

US06468099B2 Semiconductor device fabricating method 有权
公开(公告)号：US06468099B2
公开(公告)日：2002-10-22
申请号：US09941307
申请日：2001-08-29
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L218238
CPC分类号： H01L21/76202 , H01L21/76224 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method of fabricating a semiconductor device applies a LOCOS profile characteristic to an edge portion of an STI in a HV region to thereby lower compressive stress that is concentrated on the side of the STI. A field oxide film is formed so that only edge portions of HV region (active region II) may be in contact with a comparatively stiff STI, and then, a thick gate oxide film is formed on the HV region by utilizing a nitride film as a mask. After the nitride film as a mask is removed, a thin gate oxide film is formed on a LV region (an active region I in which a thin gate oxide film is formed). As a result, a thinning phenomenon of a gate oxide film at an edge portion of STI is prevented that otherwise would occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask. The present invention also prevents compromise of the operational characteristics of a resulting transistor, which otherwise would be caused by the concentration of electric field and by the hump phenomenon.

27. 发明授权

US08300195B2 Balance board and liquid crystal display having the same 失效
标题翻译：平衡板和液晶显示器相同
公开(公告)号：US08300195B2
公开(公告)日：2012-10-30
申请号：US12498190
申请日：2009-07-06
申请人： Eui-Dong Hwang , Yun-Gun Lee , Dal-Jung Kwon , Myoung-Soo Kim , Byung-Kyou Min
发明人： Eui-Dong Hwang , Yun-Gun Lee , Dal-Jung Kwon , Myoung-Soo Kim , Byung-Kyou Min
IPC分类号： G02F1/1345
CPC分类号： G02F1/133611 , G02F2001/133612
摘要： A balance board includes; a substrate, a first wire disposed on the substrate, a second wire disposed on the substrate and spaced apart from the first wire, a plurality of first balance coils connected to the first wire and which uniformly distribute a first power supply voltage, a plurality of second balance coils connected to the second wire and which uniformly distribute a second power supply voltage, and a conductive pattern disposed on the substrate and spaced apart from the first and second wires, wherein the first and second wires are disposed substantially in parallel with each other, the second wire being divided into a plurality of parts with respect to an area where the first wire and the second wire cross over one another and the plurality of parts of the second wire are connected by a plurality of jumper connectors overlapping the first wire.
摘要翻译：平衡板包括; 基板，设置在基板上的第一布线，设置在基板上并与第一布线隔开的第二布线，与第一布线连接并且均匀分布第一电源电压的多个第一平衡线圈，多个连接到第二线并且均匀分布第二电源电压的第二平衡线圈和设置在基板上并与第一和第二线分开的导电图案，其中第一和第二线基本上彼此平行地设置相对于第一线和第二线彼此交叉的区域，第二线被分成多个部分，并且第二线的多个部分通过与第一线重叠的多个跳线连接器连接。

28. 发明申请

US20090224360A1 Semiconductor integrated circuit device and method of fabricating the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20090224360A1
公开(公告)日：2009-09-10
申请号：US12379664
申请日：2009-02-26
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L23/525 , H01L23/544
CPC分类号： H01L23/544 , H01L23/5256 , H01L2223/5442 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device and a method of fabricating the same may be provided. The semiconductor integrated circuit device may include an align key pattern on a semiconductor substrate, a first passivation layer on the semiconductor substrate including the align key pattern and having a first opening exposing at least a portion of a top surface of the align key pattern, and a second passivation layer on the first passivation layer and within the first opening, wherein the second passivation layer covers the align key pattern exposed through the first opening.
摘要翻译：可以提供半导体集成电路器件及其制造方法。半导体集成电路器件可以包括半导体衬底上的对准键图案，半导体衬底上的包括对准键图案的第一钝化层，并且具有暴露对准键图案的顶表面的至少一部分的第一开口，以及所述第一钝化层和所述第一开口内的第二钝化层，其中所述第二钝化层覆盖通过所述第一开口暴露的对准键图案。

29. 发明申请

US20060024929A1 Method of forming a well in a substrate of a transistor of a semiconductor device 审中-公开
标题翻译：在半导体器件的晶体管的衬底中形成阱的方法
公开(公告)号：US20060024929A1
公开(公告)日：2006-02-02
申请号：US11170944
申请日：2005-06-30
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/337 , H01L21/425
CPC分类号： H01L21/324 , H01L21/823892
摘要： In a method of forming a well in a substrate of a transistor of a semiconductor device without an out-diffusion of impurities from the substrate, a first conductivity type impurity is implanted into the substrate. A second conductivity type impurity, which is opposite to the first conductivity type impurity, is implanted into a portion of the substrate, thereby forming a first conductivity type impurity region and a second conductivity type impurity region in the substrate. A diffusion barrier layer is formed on the substrate for preventing the first and second conductivity type impurities from being diffused out of the substrate. The substrate is heat-treated for diffusing the first and second conductivity type impurities from the first and second conductivity type impurity regions, respectively, thereby forming a first conductivity type well and a second conductivity type well in the substrate. Accordingly, an out-diffusion of the impurities from the substrate is minimized or prevented in the formation of the well.
摘要翻译：在半导体器件的晶体管的衬底中形成阱的方法中，没有杂质从衬底的扩散出来，第一导电型杂质被注入到衬底中。将与第一导电型杂质相反的第二导电型杂质注入到基板的一部分中，从而在基板中形成第一导电型杂质区和第二导电型杂质区。在基板上形成扩散阻挡层，用于防止第一和第二导电类型的杂质扩散出基板。对基板进行热处理，以分别从第一和第二导电型杂质区扩散第一和第二导电类型的杂质，从而在基板中形成井和第二导电类型井。因此，在形成阱时，使来自基板的杂质的扩散被最小化或防止。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式