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21. 发明申请

US20110014764A1 METHOD OF FORMING A DUAL-TRENCH FIELD EFFECT TRANSISTOR 有权
标题翻译：形成双重场效应晶体管的方法
公开(公告)号：US20110014764A1
公开(公告)日：2011-01-20
申请号：US12893997
申请日：2010-09-29
申请人： Bruce D. Marchant
发明人： Bruce D. Marchant
IPC分类号： H01L21/335
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095
摘要： A method of forming a field effect transistor includes forming a well region in a semiconductor region of a first conductivity type. The well region may be of a second conductivity type and have an upper surface and a lower surface. The method also includes forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region, and forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below the plurality of gate trenches. The plurality of stripe trenches may be laterally spaced from the plurality of gate trenches. The method also includes at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type. The semiconductor material of the second conductivity type may form a PN junction with a portion of the semiconductor region.
摘要翻译：形成场效应晶体管的方法包括在第一导电类型的半导体区域中形成阱区。阱区可以是第二导电类型并且具有上表面和下表面。该方法还包括形成多个栅极沟槽，其延伸到半导体区域中至阱区下表面以下的深度，以及形成多个条状沟槽，其延伸穿过阱区并进入半导体区域至多于的门沟。多个条纹沟槽可以与多个栅极沟槽横向间隔开。该方法还包括用第二导电类型的半导体材料至少部分地填充多个条形沟槽。第二导电类型的半导体材料可以与半导体区域的一部分形成PN结。

22. 发明授权

US07781835B2 Lateral drain MOSFET with improved clamping voltage control 有权
标题翻译：具有改进的钳位电压控制的侧漏MOSFET
公开(公告)号：US07781835B2
公开(公告)日：2010-08-24
申请号：US12352057
申请日：2009-01-12
申请人： Bruce D. Marchant , Dean Probst
发明人： Bruce D. Marchant , Dean Probst
IPC分类号： H01L29/94
CPC分类号： H01L29/7821 , H01L29/0878 , H01L29/1095 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66696
摘要： A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.
摘要翻译：具有衬底的横向MOSFET，在衬底上生长的第一和第二外延层和形成在栅极电介质上的栅电极，栅极电介质又形成在第二外延层的顶表面上。第二外延层包括漏极区域，其延伸到外延层的顶表面并且靠近栅电极的第一边缘，源区域延伸到第二外延层的顶表面并且接近第二外延层栅电极的边缘，在源极区的至少一部分下方的重掺杂体，以及位于第一和第二外延层的过渡区附近的栅电介质下的轻掺杂阱。重掺杂体之下的重掺杂体和第一外延区之间的PN结具有雪崩击穿电压，其基本上取决于在重掺杂体下面的第一外延层的上部的掺杂浓度。

23. 发明授权

US07382019B2 Trench gate FETs with reduced gate to drain charge 有权
标题翻译：沟槽栅极FET减少栅极到漏极电荷
公开(公告)号：US07382019B2
公开(公告)日：2008-06-03
申请号：US11116106
申请日：2005-04-26
申请人： Bruce D. Marchant , Ashok Challa
发明人： Bruce D. Marchant , Ashok Challa
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/42368 , H01L29/66734
摘要： A field effect transistor includes a trench extending into a semiconductor region. The trench has a gate dielectric lining the trench sidewalls and a gate electrode therein. A channel region in the semiconductor region extends along a sidewall of the trench. The gate dielectric has a non-uniform thickness such that a variation in thickness of the gate dielectric along at least a lower portion of the channel region is inversely dependent on a variation in doping concentration in the at least a lower portion of the channel region.
摘要翻译：场效应晶体管包括延伸到半导体区域中的沟槽。沟槽具有衬底沟槽侧壁的栅极电介质和其中的栅电极。半导体区域中的沟道区域沿沟槽的侧壁延伸。栅极电介质具有不均匀的厚度，使得沿通道区域的至少下部的栅极电介质的厚度变化与沟道区域的至少下部的掺杂浓度的变化成反比。

24. 发明授权

US08450177B2 LDMOS with self aligned vertical LDD backside drain 有权
标题翻译： LDMOS具有自对准垂直LDD背面排水
公开(公告)号：US08450177B2
公开(公告)日：2013-05-28
申请号：US13072494
申请日：2011-03-25
申请人： Bruce D. Marchant , Daniel M. Kinzer
发明人： Bruce D. Marchant , Daniel M. Kinzer
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/41766 , H01L29/66727
摘要： A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.
摘要翻译：场效应晶体管包括具有上表面和下表面的第一导电类型的半导体区域，半导体区域的下表面延伸并邻接衬底。第二导电类型的阱区域设置在半导体区域内。场效应晶体管还包括设置在阱区中的第一导电类型的源极区域和在每个阱区域上延伸并与相应的一个源极区域重叠的栅电极。每个栅极电极通过栅极电介质与下面的阱区域绝缘。第一导电类型的至少一个LDD区域设置在每两个相邻阱区域之间的半导体区域中，使得至少一个LDD区域与其所在的两个相邻的阱区域接触。沉降片区域直接位于至少一个LDD区域下方的半导体区域中，使得至少一个LDD区域和沉降弧区域沿着半导体区域的上表面和下表面之间的垂直取向定位。

25. 发明申请

US20110171798A1 LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN 有权
标题翻译： LDMOS具有自对准的垂直LDD背面排水
公开(公告)号：US20110171798A1
公开(公告)日：2011-07-14
申请号：US13072494
申请日：2011-03-25
申请人： Bruce D. Marchant , Daniel M. Kinzer
发明人： Bruce D. Marchant , Daniel M. Kinzer
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/41766 , H01L29/66727
摘要： A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.
摘要翻译：场效应晶体管包括具有上表面和下表面的第一导电类型的半导体区域，半导体区域的下表面延伸并邻接衬底。第二导电类型的阱区域设置在半导体区域内。场效应晶体管还包括设置在阱区中的第一导电类型的源极区域和在每个阱区域上延伸并与相应的一个源极区域重叠的栅电极。每个栅极电极通过栅极电介质与下面的阱区域绝缘。第一导电类型的至少一个LDD区域设置在每两个相邻阱区域之间的半导体区域中，使得至少一个LDD区域与其所在的两个相邻的阱区域接触。沉降片区域直接位于至少一个LDD区域下方的半导体区域中，使得至少一个LDD区域和沉降弧区域沿着半导体区域的上表面和下表面之间的垂直取向定位。

26. 发明授权

US07936007B2 LDMOS with self aligned vertical LDD backside drain 有权
标题翻译： LDMOS具有自对准垂直LDD背面排水
公开(公告)号：US07936007B2
公开(公告)日：2011-05-03
申请号：US12425349
申请日：2009-04-16
申请人： Bruce D. Marchant , Daniel M. Kinzer
发明人： Bruce D. Marchant , Daniel M. Kinzer
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/41766 , H01L29/66727
摘要： A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.
摘要翻译：场效应晶体管包括具有上表面和下表面的第一导电类型的半导体区域，半导体区域的下表面延伸并邻接衬底。第二导电类型的阱区域设置在半导体区域内。场效应晶体管还包括设置在阱区中的第一导电类型的源极区域和在每个阱区域上延伸并与相应的一个源极区域重叠的栅电极。每个栅极电极通过栅极电介质与下面的阱区域绝缘。第一导电类型的至少一个LDD区域设置在每两个相邻阱区域之间的半导体区域中，使得至少一个LDD区域与其所在的两个相邻的阱区域接触。沉降片区域直接位于至少一个LDD区域下方的半导体区域中，使得至少一个LDD区域和沉降弧区域沿着半导体区域的上表面和下表面之间的垂直取向定位。

27. 发明授权

US07485532B2 Method of forming trench gate FETs with reduced gate to drain charge 有权
标题翻译：形成具有减少的栅极到漏极电荷的沟槽栅极FET的方法
公开(公告)号：US07485532B2
公开(公告)日：2009-02-03
申请号：US12052135
申请日：2008-03-20
申请人： Bruce D. Marchant , Ashok Challa
发明人： Bruce D. Marchant , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/42368 , H01L29/66734
摘要： A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.
摘要翻译：一种用于形成FET的方法包括以下步骤。沟槽形成在第一导电类型的半导体区域中。在半导体区域中形成第二导电类型的阱区域。在阱区中形成第一导电类型的源极区，使得由阱区中的间隔和阱区的底表面限定的沟道区形成在沿着沟槽的相对侧壁的阱区中。沿着沟槽的相对侧壁形成具有不均匀厚度的栅极电介质层，使得栅极电介质层沿着沟道区的至少下部的厚度变化为：（i）基本上线性，和（ ii）反向依赖于沟道区域下部的掺杂浓度的变化。在每个沟槽中形成栅电极。

28. 发明授权

US06713813B2 Field effect transistor having a lateral depletion structure 有权
标题翻译：具有横向耗尽结构的场效应晶体管
公开(公告)号：US06713813B2
公开(公告)日：2004-03-30
申请号：US09774780
申请日：2001-01-30
申请人： Bruce D. Marchant
发明人： Bruce D. Marchant
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095
摘要： A field effect transistor device and a method for making a field effect transistor device are disclosed. The field effect transistor device includes a stripe trench extending from the major surface of a semiconductor substrate into the semiconductor substrate to a predetermined depth. The stripe trench contains a semiconductor material of the second conductivity type to form a PN junction at an interface formed with the semiconductor substrate.
摘要翻译：公开了一种场效应晶体管器件和一种制作场效应晶体管器件的方法。场效应晶体管器件包括从半导体衬底的主表面延伸到半导体衬底到预定深度的条状沟槽。条状沟槽包含第二导电类型的半导体材料，以在与半导体衬底形成的界面处形成PN结。

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