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21. 发明授权

US06548325B2 Wafer thickness compensation for interchip planarity 失效
公开(公告)号：US06548325B2
公开(公告)日：2003-04-15
申请号：US09953163
申请日：2001-09-17
申请人： H. Bernhard Pogge
发明人： H. Bernhard Pogge
IPC分类号： H01L2150
CPC分类号： H01L24/95 , H01L25/0655 , H01L25/50 , H01L29/0657 , H01L2224/13022 , H01L2224/81141 , H01L2224/95136 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/04953 , H01L2924/10158 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/3025 , H01L2924/00
摘要： In a very dense integrated circuit package, including a carrier having a topography of projections with sloping sides for supporting individual semiconductor circuit chips with a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier, a method for compensating for variations in chip thickness by controlling the width of recesses in bottom surface topography so that alignment on the carrier projections will elevate thinner chips so that the device side of the chips are co-planar.

22. 发明授权

US6066513A Process for precise multichip integration and product thereof 失效
标题翻译：精确多芯片整合的过程及其产品
公开(公告)号：US6066513A
公开(公告)日：2000-05-23
申请号：US165280
申请日：1998-10-02
申请人： H. Bernhard Pogge , Subramania S. Iyer
发明人： H. Bernhard Pogge , Subramania S. Iyer
IPC分类号： H01L21/306 , H01L21/68 , H01L21/98 , H01L21/44
CPC分类号： H01L21/6835 , H01L21/30608 , H01L25/50 , H01L2221/68313 , H01L2221/68359 , H01L2224/83136 , H01L2224/83894 , H01L2924/3025 , Y10S438/975
摘要： Process for making an integrated circuit module and product thereof including a carrier supporting a plurality of precisely aligned semiconductor circuit chips having uniform thicknesses.
摘要翻译：用于制造集成电路模块及其产品的方法，其包括支撑具有均匀厚度的多个精确对准的半导体电路芯片的载体。

23. 发明授权

US5998868A Very dense chip package 失效
标题翻译：非常密集的芯片封装
公开(公告)号：US5998868A
公开(公告)日：1999-12-07
申请号：US18736
申请日：1998-02-04
申请人： H. Bernhard Pogge , Bijan Davari , Johann Greschner , Howard L. Kalter
发明人： H. Bernhard Pogge , Bijan Davari , Johann Greschner , Howard L. Kalter
IPC分类号： H01L21/762 , H01L21/98 , H01L23/13 , H01L25/065 , H01L29/06 , H01L29/04
CPC分类号： H01L25/50 , H01L21/7624 , H01L21/76264 , H01L23/13 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0655 , H01L2224/13022 , H01L2224/24137 , H01L2224/73267 , H01L2224/81141 , H01L2224/83141 , H01L2224/97 , H01L29/0657 , H01L2924/01019 , H01L2924/01055 , H01L2924/10158 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15156 , H01L2924/15157 , H01L2924/15165
摘要： An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m
摘要翻译：集成电路封装或布置包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。相邻芯片的顶面基本上位于距离大于0.0μm的平面中。相邻的芯片由间隙G分开，间距约为1μm〜约100μm。金属互连设置在顶面和间隙之上。优选地，互连在间隙上具有逐渐的斜率。

24. 发明授权

US5899703A Method for chip testing 失效
标题翻译：芯片测试方法
公开(公告)号：US5899703A
公开(公告)日：1999-05-04
申请号：US827207
申请日：1997-03-28
申请人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
发明人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
IPC分类号： G01R31/28 , H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , G01R31/2884
摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.
摘要翻译：大面积芯片功能在制造过程的中间级别进行测试。实现了在芯片上沉积绝缘体材料层的工艺顺序。然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。其他通孔仍然用绝缘体覆盖。然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。与测试电路的连接在绝缘体层上具有牺牲金属层。测试后去除牺牲金属层和绝缘体层。在线路处理后端完成之后分离芯片的过程中，划线测试电路。

25. 发明授权

US5081439A Thin film resistor and method for producing same 失效
标题翻译：薄膜电阻器及其制造方法
公开(公告)号：US5081439A
公开(公告)日：1992-01-14
申请号：US615938
申请日：1990-11-16
申请人： Wesley C. Natzle , H. Bernhard Pogge , Kerry L. Batdorf
发明人： Wesley C. Natzle , H. Bernhard Pogge , Kerry L. Batdorf
IPC分类号： H01C7/00 , H01C17/242 , H01L27/00 , H01L27/01
CPC分类号： H01C17/242 , Y10T29/49099
摘要： A planar film resistor is trimmable by a laser beam. A pair of electrodes are spaced apart on a substrate and make contact with a film of resistive material disposed therebetween. The resistive material includes a laser produced trim region disposed internally to all boundaries of the resistive material, and extends through the thickness of said film. The trim region has an elongated dimension which is orthogonal to the most direct current path between the electrodes. In a preferred embodiment, the resistive material is covered by a passivating layer and is trimmed after the passivating layer is in place.

26. 发明授权

US07344959B1 Metal filled through via structure for providing vertical wafer-to-wafer interconnection 有权
标题翻译：通过通孔结构的金属填充，用于提供垂直的晶片到晶片互连
公开(公告)号：US07344959B1
公开(公告)日：2008-03-18
申请号：US11459784
申请日：2006-07-25
申请人： H. Bernhard Pogge , Roy R. Yu
发明人： H. Bernhard Pogge , Roy R. Yu
IPC分类号： H01L21/30 , H01L21/44
CPC分类号： H01L24/90 , H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/28 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/13009 , H01L2224/13099 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/83194 , H01L2224/838 , H01L2224/9201 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/1306 , H01L2924/15787 , H01L2924/00014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/05552
摘要： A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.
摘要翻译：提供一种制造用于提供垂直晶片到晶片互连结构的通孔连接的方法以及通过该方法形成的垂直互连结构。本发明的方法仅使用金属螺柱进行垂直连接，因此金属螺柱不产生α辐射。本发明的方法包括插入步骤，加热步骤，变薄步骤和背面处理。

27. 发明授权

US07049695B1 Method and device for heat dissipation in semiconductor modules 有权
标题翻译：半导体模块散热方法和装置
公开(公告)号：US07049695B1
公开(公告)日：2006-05-23
申请号：US10905643
申请日：2005-01-14
申请人： H. Bernhard Pogge
发明人： H. Bernhard Pogge
IPC分类号： H01L23/12 , H01L23/10 , H05K7/20
CPC分类号： H01L23/3735 , H01L23/3677 , H01L23/3738 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/00 , H01L2224/0401
摘要： A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.
摘要翻译：提供了用于从半导体器件芯片散热的结构和方法。介电材料（例如聚酰亚胺）的第一层形成在散热器（通常为Si）的前侧。通过该第一层形成多个开口; 开口用金属（通常为Cu）填充，从而形成延伸穿过第一层的金属螺柱。第二层金属形成在器件芯片的背面。然后在接合工艺中接合第一层和第二层，由此形成金属柱与第二层接触的接合层。因此，接合层提供从芯片到散热器的导热路径。

28. 发明授权

US6087199A Method for fabricating a very dense chip package 失效
标题翻译：制造非常密集的芯片封装的方法
公开(公告)号：US6087199A
公开(公告)日：2000-07-11
申请号：US18737
申请日：1998-02-04
申请人： H. Bernhard Pogge , Bijan Davari , Johann Greschner , Howard L. Kalter
发明人： H. Bernhard Pogge , Bijan Davari , Johann Greschner , Howard L. Kalter
IPC分类号： H01L21/768 , H01L21/98 , H01L23/13 , H01L25/065 , H01L29/06 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/76838 , H01L23/13 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0655 , H01L2224/13022 , H01L2224/18 , H01L2224/24137 , H01L2224/73267 , H01L2224/83141 , H01L2224/97 , H01L29/0657 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/10158 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15156 , H01L2924/15157 , H01L2924/15165 , H01L2924/3025
摘要： A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m
摘要翻译：一种用于制造集成电路封装或布置的方法包括提供具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。设置芯片使得相邻芯片的顶面基本上位于大于0.0μm的距离上的平面中。载体的布置和尺寸使得相邻的芯片由间隙G分隔开，或间隔在1μm×100μm的范围内。在顶面和间隙上设有金属互连。优选地，互连在间隙上具有逐渐的斜率。

29. 发明授权

US4137103A Silicon integrated circuit region containing implanted arsenic and germanium 失效
标题翻译：硅集成电路区域包含植入砷和锗
公开(公告)号：US4137103A
公开(公告)日：1979-01-30
申请号：US908322
申请日：1978-05-22
申请人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
发明人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
IPC分类号： H01L21/265 , H01L29/167 , H01L21/203
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/167 , Y10S148/024 , Y10S148/061 , Y10S438/938
摘要： A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 .times. 10.sup.-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 .times. 10.sup.-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

30. 发明授权

US4111719A Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium 失效
标题翻译：通过阿根廷和德国的双重植入来最小化硅中的杂质错位
公开(公告)号：US4111719A
公开(公告)日：1978-09-05
申请号：US748035
申请日：1976-12-06
申请人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
发明人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
IPC分类号： H01L21/265 , H01L29/167 , H01L9/10
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/167 , Y10S148/024 , Y10S148/061 , Y10S438/938
摘要： A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 .times. 10.sup.-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 .times. 10.sup.-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.
摘要翻译：一种用于在硅衬底中形成N导电型区域的方法，其包括离子注入砷以形成所述衬底中的砷原子浓度至少为1×10 -2 As原子/底物中的总原子，并将离子注入锗所述衬底区域。尽管砷的原子半径非常接近于硅的原子半径 - 砷的半径只有0.5％ - 当基片中至少有1×10-2个原子/总原子的高砷原子浓度被引入到底物，并且这样高的浓度仅在砷被离子注入时才可能，则将发生原子失配位错。植入的锗原子补偿硅中的晶格应变以最小化位错。

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