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21. 发明授权

US5137842A Stacked H-cell capacitor and process to fabricate same 失效
标题翻译：堆叠H电池电容器和工艺制造相同
公开(公告)号：US5137842A
公开(公告)日：1992-08-11
申请号：US699291
申请日：1991-05-10
申请人： Hiang C. Chan , Pierre Fazan
发明人： Hiang C. Chan , Pierre Fazan
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译：修改现有的堆叠电容器制造工艺以构建称为堆叠H电池（SHC）的三维叠层电容器。 SHC设计定义了在本发明中用于DRAM处理的电容器存储单元。 SHC由具有H形横截面上部的多晶硅存储节点结构构成，下部向下延伸并通过埋入触点与有源区接触。多晶硅存储节点结构由多晶硅覆盖，电介质夹在其间以形成完整的SHC电容器。具有H形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。

22. 发明授权

US5061650A Method for formation of a stacked capacitor 失效
标题翻译：叠层电容器的形成方法
公开(公告)号：US5061650A
公开(公告)日：1991-10-29
申请号：US643835
申请日：1991-01-17
申请人： Charles H. Dennison , Hiang Chan , Yauh-Ching Liu , Pierre Fazan , Howard E. Rhodes
发明人： Charles H. Dennison , Hiang Chan , Yauh-Ching Liu , Pierre Fazan , Howard E. Rhodes
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817
摘要： A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied. The third dielectric layer is then anisotropicallly etched to provide a first dielectric wall extending upwardly from the first conductive layer adjacent the first conductive wall. A third electrically conductive layer is next applied over the first conductive and dielectric walls. It is then anisotropically etched to provide a second electrically conductive wall extending upwardly from the first conductive layer adjacent the first dielectric wall. The first dielectric wall is then etched from the wafer. A capacitor dielectric layer is then applied, followed by a fourth electrically conductive layer to form an upper capacitor plate.
摘要翻译：公开了一种在半导体晶片上形成电容器的方法。将第一导电层施加在晶片顶部并接合暴露的有源区。接下来应用第一电介质层。然后将第一介电层和导电层图案化以限定下电容器板的轮廓。然后施加具有比第一介质层慢的蚀刻速率的第二介电层，并将其平坦化或以其它方式蚀刻到第一介电层。然后将第一电介质层向下蚀刻到第一导电层，以产生围绕较低电容器板轮廓的第二介电材料的向上突出的壁。然后施加第二导电层。然后对其进行各向异性蚀刻以提供从第一导电层向上延伸的第一导电壁。然后施加第三介电层。然后对第三电介质层进行各向异性蚀刻以提供从邻近第一导电壁的第一导电层向上延伸的第一电介质壁。接着将第三导电层施加在第一导电和电介质壁上。然后对其进行各向异性蚀刻以提供从邻近第一介电壁的第一导电层向上延伸的第二导电壁。然后从晶片蚀刻第一电介质壁。然后施加电容器介电层，随后是第四导电层以形成上电容器板。

23. 发明授权

US08518774B2 Manufacturing process for zero-capacitor random access memory circuits 有权
标题翻译：零电容随机存取存储器电路的制造过程
公开(公告)号：US08518774B2
公开(公告)日：2013-08-27
申请号：US12053398
申请日：2008-03-21
申请人： Pierre Fazan
发明人： Pierre Fazan
IPC分类号： H01L29/06
CPC分类号： H01L27/10805 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/10847 , H01L27/1203 , H01L29/7841
摘要： Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.
摘要翻译：用于制造独立存储器件的制造工艺流程的实施例，其可以实现4F2或5F2的数量级的位单元尺寸，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共漏极晶体管阵列有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

24. 发明申请

US20080165577A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080165577A1
公开(公告)日：2008-07-10
申请号：US11904978
申请日：2007-09-28
申请人： Pierre Fazan , Serguel Okhonin
发明人： Pierre Fazan , Serguel Okhonin
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

25. 发明申请

US20070109896A1 Data storage device and refreshing method for use with such device 有权
公开(公告)号：US20070109896A1
公开(公告)日：2007-05-17
申请号：US11649945
申请日：2007-01-05
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

26. 发明授权

US06969662B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06969662B2
公开(公告)日：2005-11-29
申请号：US10450238
申请日：2002-06-05
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , H01L21/336
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。主体22中的净电荷的大小可以通过施加到晶体管的输入信号进行调整，并且可以通过在栅极28和栅极28之间施加电压信号来至少部分地抵消由输入信号调节净电荷漏极22和源极18与漏极22之间。

27. 发明申请

US20050063224A1 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
标题翻译：用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术
公开(公告)号：US20050063224A1
公开(公告)日：2005-03-24
申请号：US10941692
申请日：2004-09-15
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/404 , H01L27/108 , G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.
摘要翻译：这里描述和说明了许多发明。在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储单元很少或没有电流/功耗电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。

28. 发明授权

US6090670A Highly efficient transistor for fast programming of flash memories 失效
标题翻译：高效晶体管，用于快速编程闪存
公开(公告)号：US6090670A
公开(公告)日：2000-07-18
申请号：US929138
申请日：1997-09-05
申请人： Gurtej Singh Sandhu , Pierre Fazan
发明人： Gurtej Singh Sandhu , Pierre Fazan
IPC分类号： H01L29/423 , H01L29/788 , H01L21/336 , H01L29/76 , H01L29/80
CPC分类号： H01L29/7885 , H01L29/42324
摘要： In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region. The surface of the semiconductor substrate can be curved in the vicinity of the drain of the asymmetric transistor in order to permit the momentum of the charge carriers to facilitate penetration of the charge carriers into the gate.
摘要翻译：在用于在半导体衬底上形成晶体管结构的半导体制造方法中，在半导体衬底上也形成氮化物层。在半导体衬底的区域上形成栅氧化层。栅极氧化物层在氮化物层上方具有相对较薄的氧化物区域，并且在邻近氮化物层的衬底上方相对较厚的氧化物区域。晶体管栅极形成在相对较薄的氧化物区域上方并在相对较厚的氧化物区域上延伸。因此，如此形成的晶体管是不对称的。在相对较厚的氧化物区域附近形成第一晶体管有源区，并且在相对较薄的氧化物区域附近形成第二晶体管有源区。可以通过半导体衬底的快速热氮化形成氮化物层。相对较薄的氧化物区域可以是相对较薄的氧化物区域的一半厚度。半导体衬底的表面可以在不对称晶体管的漏极附近弯曲，以允许电荷载流子的动量促进电荷载流子进入栅极。

29. 发明授权

US5939333A Silicon nitride deposition method 失效
标题翻译：氮化硅沉积法
公开(公告)号：US5939333A
公开(公告)日：1999-08-17
申请号：US655728
申请日：1996-05-30
申请人： Kelly T. Hurley , Li Li , Pierre Fazan , Zhiqiang Wu
发明人： Kelly T. Hurley , Li Li , Pierre Fazan , Zhiqiang Wu
IPC分类号： C23C16/02 , C23C16/34 , H01L21/314 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3144 , C23C16/0272 , C23C16/345 , H01L21/76224
摘要： A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces of the substrate surface resulting in a substantially native oxide free uniform predeposited silicon substrate surface. Thereafter, a silicon nitride layer is deposited on the predeposited silicon substrate surface after the silicon predeposition. Further, another silicon nitride deposition method includes providing a silicon based substrate surface. The substrate surface is nitridated in an atmosphere of dimethylhydrazine, and thereafter, a silicon nitride layer is deposited on the nitridated surface. The nitridation of the substrate surface results in a thickness less than three monolayers of silicon nitride.
摘要翻译：氮化硅沉积方法包括提供包括一个或多个部件表面的基板表面。至少单层硅预沉积在衬底表面的一个或多个组件表面上，导致基本上无氧化的均匀的预沉积硅衬底表面。此后，在硅预沉积之后，在预沉积的硅衬底表面上沉积氮化硅层。此外，另一种氮化硅沉积方法包括提供硅基衬底表面。将基板表面在二甲基肼的气氛中氮化，然后在氮化表面上沉积氮化硅层。衬底表面的氮化导致厚度小于三层氮化硅单层。

30. 发明授权

US5866453A Etch process for aligning a capacitor structure and an adjacent contact corridor 失效
标题翻译：用于对齐电容器结构和相邻触点走廊的蚀刻工艺
公开(公告)号：US5866453A
公开(公告)日：1999-02-02
申请号：US527924
申请日：1995-09-14
申请人： Kirk D. Prall , Pierre Fazan , Trung Doan , Tyler Lowrey
发明人： Kirk D. Prall , Pierre Fazan , Trung Doan , Tyler Lowrey
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10808
摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.
摘要翻译：用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。蚀刻工艺在半导体衬底上形成的电容器结构中实现。电容器结构包括第一导体，第一导体上的电介质层和电介质层上的第二导体。第二导体具有横向邻近并远离第一导体延伸的水平区域。蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。或者，使用单个各向同性蚀刻去除第二导体的水平区域。

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