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21. 发明授权

US07882338B2 Method, system and computer program product for an implicit predicted return from a predicted subroutine 失效
标题翻译：用于预测子程序的隐式预测回报的方法，系统和计算机程序产品
公开(公告)号：US07882338B2
公开(公告)日：2011-02-01
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito, III , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito, III , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/32
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译：提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

22. 发明授权

US09021240B2 System and method for Controlling restarting of instruction fetching using speculative address computations 有权
标题翻译：使用推测地址计算控制指令重写的系统和方法
公开(公告)号：US09021240B2
公开(公告)日：2015-04-28
申请号：US12035911
申请日：2008-02-22
申请人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3861 , G06F9/322 , G06F9/3804 , G06F9/3806 , G06F9/3838 , G06F9/3842 , G06F9/3867
摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.
摘要翻译：提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。系统还包括目标选择逻辑，包括循环队列。目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

23. 发明申请

US20090217017A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY 审中-公开
标题翻译：用于最小化分支预测延迟的方法，系统和计算机程序产品
公开(公告)号：US20090217017A1
公开(公告)日：2009-08-27
申请号：US12037137
申请日：2008-02-26
申请人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
发明人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3806 , G06F9/3814
摘要： A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.
摘要翻译：提供了一种用于在流水线计算机处理环境中最小化分支预测延迟的方法，系统和计算机程序产品。该方法包括利用转移指令地址和存储在分支目标缓冲器（BTB）中的对应目标地址来检测分支回路。该方法还包括将分支循环读取到预解码指令缓冲器中，并对分支循环进行限定循环锁定。该方法还包括将形成分支循环的指令流锁定在预解码指令缓冲器中，并且处理来自缓冲器的限定分支循环指令并且断电与BTB相关联的指令获取和分支预测逻辑（BPL）。

24. 发明授权

US08176406B2 Hard error detection 有权
标题翻译：硬错误检测
公开(公告)号：US08176406B2
公开(公告)日：2012-05-08
申请号：US12051367
申请日：2008-03-19
申请人： Brian R. Prasky , Khary J. Alexander , James J. Bonanno
发明人： Brian R. Prasky , Khary J. Alexander , James J. Bonanno
IPC分类号： G06F7/02
CPC分类号： G06F11/0751 , G06F9/30105 , G06F9/30141 , G06F9/3861 , G06F11/0721
摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.
摘要翻译：提供了一种错误检测系统。该系统包括包括一个或多个数据条目的数据阵列。复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。索引生成器选择性地增加引用数据数组的索引。第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。误差发生器根据第一个比较器的结果产生一个误差信号。

25. 发明申请

US20090210661A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE 失效
标题翻译：方法，系统和计算机程序产品预测从预测的SUBROUTINE返回
公开(公告)号：US20090210661A1
公开(公告)日：2009-08-20
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译：提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

26. 发明申请

US20090240977A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR HARD ERROR DETECTION 有权
标题翻译：用于硬度错误检测的方法，系统和计算机程序产品
公开(公告)号：US20090240977A1
公开(公告)日：2009-09-24
申请号：US12051367
申请日：2008-03-19
申请人： Brian R. Prasky , Khary J. Alexander , James J. Bonanno
发明人： Brian R. Prasky , Khary J. Alexander , James J. Bonanno
IPC分类号： G06F11/14
CPC分类号： G06F11/0751 , G06F9/30105 , G06F9/30141 , G06F9/3861 , G06F11/0721
摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.
摘要翻译：提供了一种错误检测系统。该系统包括包括一个或多个数据条目的数据阵列。复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。索引生成器选择性地增加引用数据数组的索引。第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。误差发生器根据第一个比较器的结果产生一个误差信号。

27. 发明申请

US20090217015A1 SYSTEM AND METHOD FOR CONTROLLING RESTARTING OF INSTRUCTION FETCHING USING SPECULATIVE ADDRESS COMPUTATIONS 有权
标题翻译：使用分布式地址计算来控制指导性重击的系统和方法
公开(公告)号：US20090217015A1
公开(公告)日：2009-08-27
申请号：US12035911
申请日：2008-02-22
申请人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/322 , G06F9/3804 , G06F9/3806 , G06F9/3838 , G06F9/3842 , G06F9/3867
摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.
摘要翻译：提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。系统还包括目标选择逻辑，包括循环队列。目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

28. 发明申请

US20130339665A1 COLLISION-BASED ALTERNATE HASHING 有权
标题翻译：基于冲突的替代洗涤
公开(公告)号：US20130339665A1
公开(公告)日：2013-12-19
申请号：US13524139
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3806 , G06F9/3804 , G06F9/3808 , G06F9/3814
摘要： Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.
摘要翻译：实施例涉及基于冲突的交替散列。一方面包括接收输入指令地址。另一方面包括基于输入指令地址的散列来确定历史表中是否存在输入指令地址的条目。另一方面包括基于确定输入指令地址的条目存在于历史表中，确定输入指令地址是否匹配所确定条目中的地址标签。另一方面包括基于确定输入指令地址与所确定的条目中的地址标签不匹配，确定对于输入指令地址是否存在冲突。另一方面包括基于确定对于输入指令地址存在冲突，使用替代散列缓冲器激活输入指令地址的替换散列。

29. 发明授权

US09250913B2 Collision-based alternate hashing 有权
标题翻译：基于碰撞的交替散列
公开(公告)号：US09250913B2
公开(公告)日：2016-02-02
申请号：US13524139
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3804 , G06F9/3808 , G06F9/3814
摘要： Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.
摘要翻译：实施例涉及基于冲突的交替散列。一方面包括接收输入指令地址。另一方面包括基于输入指令地址的散列来确定历史表中是否存在输入指令地址的条目。另一方面包括基于确定输入指令地址的条目存在于历史表中，确定输入指令地址是否匹配所确定条目中的地址标签。另一方面包括基于确定输入指令地址与所确定的条目中的地址标签不匹配，确定对于输入指令地址是否存在冲突。另一方面包括基于确定对于输入指令地址存在冲突，使用替代散列缓冲器激活输入指令地址的替换散列。

30. 发明授权

US09442737B2 Restricting processing within a processor to facilitate transaction completion 有权
公开(公告)号：US09442737B2
公开(公告)日：2016-09-13
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52 , G06F9/46
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

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