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21. 发明申请

US20130028022A1 DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE 有权
标题翻译：记忆设备中的动态程序窗口确定
公开(公告)号：US20130028022A1
公开(公告)日：2013-01-31
申请号：US13190911
申请日：2011-07-26
申请人： Tommaso VALI , Giovanni Santin , Massimo Rossini , William H. Radke , Violante Moschiano
发明人： Tommaso VALI , Giovanni Santin , Massimo Rossini , William H. Radke , Violante Moschiano
IPC分类号： G11C16/10
CPC分类号： G11C16/3436 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/3418 , G11C16/3422
摘要： Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.
摘要翻译：公开了用于确定程序窗口和存储器件的方法。用于确定程序窗口的一种这样的方法测量由特定状态经历的程序干扰量，并且响应于程序干扰量确定程序窗口。

22. 发明申请

US20120307564A1 METHOD FOR KINK COMPENSATION IN A MEMORY 有权
标题翻译：闪存补偿方法
公开(公告)号：US20120307564A1
公开(公告)日：2012-12-06
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

23. 发明授权

US08264882B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/34 , G11C16/28 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

24. 发明授权

US08194448B2 Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully programmed 有权
标题翻译：在相邻页面未完全编程的情况下，减少多位NAND闪存中FG-FG干扰的技术
公开(公告)号：US08194448B2
公开(公告)日：2012-06-05
申请号：US12647317
申请日：2009-12-24
申请人： Violante Moschiano , Giovanni Santin
发明人： Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed.
摘要翻译：提供了一种在编程NAND闪速存储器中减少浮置栅极 - 浮动栅极干扰的方法。在对存储器单元的上部页进行编程之前，该方法包括检查邻近存储器单元的相邻页面是否被编程。该方法可以编程尚未被编程的近的存储器单元的相邻页面。

25. 发明申请

US20110194350A1 COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE 有权
标题翻译：补充存储器件中的反向图案效应
公开(公告)号：US20110194350A1
公开(公告)日：2011-08-11
申请号：US13090754
申请日：2011-04-20
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

26. 发明授权

US07944757B2 Non-volatile multilevel memory cell programming 有权
标题翻译：非易失性多层存储器单元编程
公开(公告)号：US07944757B2
公开(公告)日：2011-05-17
申请号：US12718290
申请日：2010-03-05
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali , Massimo Rossini
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali , Massimo Rossini
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译：本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。

27. 发明授权

US07936606B2 Compensation of back pattern effect in a memory device 有权
标题翻译：在存储器件中补偿背面图案效果
公开(公告)号：US07936606B2
公开(公告)日：2011-05-03
申请号：US12108067
申请日：2008-04-23
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of provided embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在一个或多个所提供的实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

28. 发明申请

US20110063920A1 SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE 有权
标题翻译：感知记忆设备中的所有位线结构
公开(公告)号：US20110063920A1
公开(公告)日：2011-03-17
申请号：US12561692
申请日：2009-09-17
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali
IPC分类号： G11C16/06 , G11C7/10 , G11C7/00
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C7/12 , G11C16/24
摘要： Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
摘要翻译：公开了用于感测，存储器件和存储器系统的方法。一种用于感测的方法包括将全位线架构的位线充电到预充电电压，选择字线以及对位线进行感测操作。在对第一选定字线的存储单元进行感测操作完成之后，在选择第二字线的同时，在位线上保持预充电电压。

29. 发明授权

US07848158B2 Methods and apparatuses for programming flash memory using modulated pulses 有权
标题翻译：使用调制脉冲编程闪存的方法和装置
公开(公告)号：US07848158B2
公开(公告)日：2010-12-07
申请号：US12151265
申请日：2008-05-05
申请人： Violante Moschiano , Tommaso Vali , Giovanni Santin , Walter Di Francesco
发明人： Violante Moschiano , Tommaso Vali , Giovanni Santin , Walter Di Francesco
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C16/12
摘要： Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. An apparatus may have a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. The apparatus may have a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatuses may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. An apparatus may generate a sequence of pulses, apply the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulate one or more of pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.
摘要翻译：公开了通过使用调制脉冲来编程非易失性半导体存储器件的方法和装置。装置可以具有脉冲发生器，以产生脉冲序列并设置非易失性存储单元的阈值电压和脉冲耦合器。该装置可以具有能够验证阈值电压被设置在目标阈值电压的可接受电压范围内的阈值校验器。某些设备中的脉冲宽度调制器可以在编程快速位时在序列的早期调制脉冲持续时间，而在编程慢位时可以在序列的后期调制脉冲持续时间。设备可以产生脉冲序列，将脉冲序列应用于存储器单元以设置存储器单元的阈值电压，并且调制脉冲持续时间，脉冲间隔时间和步长的参数中的一个或多个脉冲电压幅度。

30. 发明授权

US07639534B2 Device, system, and method of bit line selection of a flash memory 有权
标题翻译： Flash存储器的位线选择的设备，系统和方法
公开(公告)号：US07639534B2
公开(公告)日：2009-12-29
申请号：US11860949
申请日：2007-09-25
申请人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。

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