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21. 发明授权

US08516502B2 Performing java interrupt with two program counters 有权
标题翻译：用两个程序计数器执行java中断
公开(公告)号：US08516502B2
公开(公告)日：2013-08-20
申请号：US11741237
申请日：2007-04-27
申请人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
发明人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/455 , G06F9/45
CPC分类号： G06F9/4812
摘要： A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).
摘要翻译：一种用于执行Java中断的方法和系统。至少一些说明性实施例是包括基于第一程序计数器执行在堆栈上具有上下文的线程的方法，在执行线程的同时检测中断（其中线程的执行被暂停），并且执行方法部分处理中断（其中基于第一程序计数器在堆栈上执行方法部分，并且其中方法部分的执行期间的上下文与执行线程期间相同）。

22. 发明授权

US08046748B2 Method and system to emulate an M-bit instruction set 有权
标题翻译：一种用于模拟M位指令集的方法和系统
公开(公告)号：US08046748B2
公开(公告)日：2011-10-25
申请号：US11188310
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.
摘要翻译：一种模拟M位指令集的方法和系统。说明性实施例中的至少一些是一种方法，包括获取指令的至少一部分（来自第一指令集的不是由处理器直接执行的指令），索引到索引位置（基于索引位置）在指令的至少一部分上），执行由处理器直接执行的第一系列指令（由索引位置处的表指向的第一系列指令），从而模拟来自第一指令的指令的执行组。

23. 发明申请

US20080134322A1 Micro-Sequence Based Security Model 有权
标题翻译：基于微序列的安全模型
公开(公告)号：US20080134322A1
公开(公告)日：2008-06-05
申请号：US11677367
申请日：2007-02-21
申请人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
发明人： Gerard Chauvel , Gilbert Cabillic , Jean-Philippe Lesot
IPC分类号： H04L9/32
CPC分类号： G06F9/4812
摘要： The problems noted above are solved in large part by a method and system for implementing a micro-sequence based security model. Specifically, micro-sequences and JSM hardware resources may be employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. A method is disclosed, comprising defining a micro-sequence based security policy. The method also comprises determining whether an instruction accesses a privileged resource. When not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.
摘要翻译：上述问题在很大程度上是由实现基于微序列的安全模型的方法和系统来解决的。具体来说，可以使用微序列和JSM硬件资源来构建应用程序不可见的安全模型，并且当存在内存限制时，通过实现微序列安全触发器来扩展JSM代码中的复杂安全模型。公开了一种方法，包括定义基于微序列的安全策略。该方法还包括确定指令是否访问特权资源。当尚未处于特权模式并且未执行微序列时，将基于微序列的安全策略应用于根据安全策略控制对特权资源的访问的指令。

24. 发明申请

US20060026571A1 Method and system of control flow graph construction 有权
公开(公告)号：US20060026571A1
公开(公告)日：2006-02-02
申请号：US11189367
申请日：2005-07-26
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.

25. 发明申请

US20060026400A1 Automatic operand load, modify and store 有权
公开(公告)号：US20060026400A1
公开(公告)日：2006-02-02
申请号：US11188311
申请日：2005-07-25
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

26. 发明申请

US20060026404A1 Method and system to construct a data-flow analyzer for a bytecode verfier 有权
标题翻译：构建一个字节码verfier的数据流分析器的方法和系统
公开(公告)号：US20060026404A1
公开(公告)日：2006-02-02
申请号：US11188502
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
摘要翻译：上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。

27. 发明申请

US20060025986A1 Method and system to emulate an M-bit instruction set 有权
标题翻译：用于模拟M位指令集的方法和系统
公开(公告)号：US20060025986A1
公开(公告)日：2006-02-02
申请号：US11188310
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/455
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.
摘要翻译：一种模拟M位指令集的方法和系统。说明性实施例中的至少一些是一种方法，包括获取指令的至少一部分（来自第一指令集的不是由处理器直接执行的指令），索引到索引位置（基于索引位置）在指令的至少一部分上），执行由处理器直接执行的第一系列指令（由索引位置处的表指向的第一系列指令），从而模拟来自第一指令的指令的执行组。

28. 发明授权

US08078842B2 Removing local RAM size limitations when executing software code 有权
标题翻译：执行软件代码时，删除本地RAM大小限制
公开(公告)号：US08078842B2
公开(公告)日：2011-12-13
申请号：US11186036
申请日：2005-07-21
申请人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
发明人： Gilbert Cabillic , Gerard Chauvel , Jean-Philippe Lesot
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译：一种电子设备，包括包括单独指令和第一组指令的处理器。该设备还包括外部耦合到处理器的存储器以及第二组指令。当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。

29. 发明授权

US07743384B2 Method and system for implementing an interrupt handler 有权
标题翻译：用于实现中断处理程序的方法和系统
公开(公告)号：US07743384B2
公开(公告)日：2010-06-22
申请号：US11189422
申请日：2005-07-26
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Gerard Chauvel
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class defines a handler method for an interrupt and an execution flow execution method that overrides the execution flow execution method of the execution flow class. An interrupt handler object is instantiated using the interrupt handler class, the constructor creates an execution flow context for the handler method, and when the interrupt is signaled, the JVM invokes a native execution flow activation method in the execution flow scheduler to switch to the handler execution flow context and the execution flow execution method to initiate execution of the handler method.
摘要翻译：提供了一种用于Java中的中断处理系统，其中包括执行流类，执行流调度程序，Java虚拟机（JVM）和扩展执行流类的中断处理程序类。执行流类定义了执行流执行方法和创建执行流上下文的构造函数。中断处理程序类定义了一个中断处理程序方法和一个执行流执行方法，该方法覆盖执行流类的执行流执行方法。中断处理程序对象使用中断处理程序类进行实例化，构造函数为处理程序方法创建一个执行流程上下文，当发出中断信号时，JVM会调用执行流调度程序中的本机执行流程激活方法来切换到处理程序执行流程上下文和执行流执行方法来启动处理程序方法的执行。

30. 发明授权

US07260682B2 Cache memory usable as scratch pad storage 有权
标题翻译：高速缓存可用作临时存储区
公开(公告)号：US07260682B2
公开(公告)日：2007-08-21
申请号：US11188668
申请日：2005-07-25
申请人： Jean-Philippe Lesot , Gilbert Cabillic , Gerard Chauvel
发明人： Jean-Philippe Lesot , Gilbert Cabillic , Gerard Chauvel
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.
摘要翻译：适于耦合到外部存储器的处理器。处理器包括控制器和数据存储器。数据存储器可用于存储局部变量和临时数据，并且可配置为在高速缓存策略模式中运行，其中未命中导致外部存储器的访问或暂存不导致的暂存器策略模式访问外部存储器。数据存储器包括第一和第二部分，并且其中只有一个所述部分在一次存储所述局部变量的时间是有效的。当活动部分对于额外的局部变量不具有足够的容量时，另一部分成为用于存储局部变量的活动部分。当一部分是活动部分时，另一部分用于存储临时数据，并且这样的其他部分足够大以容纳临时数据。

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