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21. 发明授权

US07454538B2 Latency insensitive FIFO signaling protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US07454538B2
公开(公告)日：2008-11-18
申请号：US11128135
申请日：2005-05-11
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

22. 发明授权

US07404042B2 Handling cache miss in an instruction crossing a cache line boundary 有权
标题翻译：处理高速缓存未命中，跨越高速缓存线边界
公开(公告)号：US07404042B2
公开(公告)日：2008-07-22
申请号：US11132749
申请日：2005-05-18
申请人： Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
发明人： Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译：处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。指令可能会跨越缓存行边界。流水线处理两个地址以恢复完整的边界交叉指令。在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

23. 发明授权

US07152155B2 System and method of correcting a branch misprediction 有权
标题翻译：校正分支错误预测的系统和方法
公开(公告)号：US07152155B2
公开(公告)日：2006-12-19
申请号：US11061981
申请日：2005-02-18
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re-fetched and executed.
摘要翻译：当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。纠正分支预测，并且重新获取并执行分支指令和比分支指令更早的所有刷新指令。

24. 发明授权

US06948053B2 Efficiently calculating a branch target address 失效
标题翻译：有效地计算分支目标地址
公开(公告)号：US06948053B2
公开(公告)日：2005-09-20
申请号：US10082144
申请日：2002-02-25
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38
CPC分类号： G06F9/322 , G06F9/324 , G06F9/3804
摘要： A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n−1 lower order bits of the branch target address to form the complete branch target address.
摘要翻译：一种用于计算分支目标地址的方法和系统。在从存储器取出分支指令时，可以在将转移指令存储在指令高速缓存中之前将分支目标地址的n-1个较低位进行预先计算并存储在转移指令中。在从指令高速缓存中检索分支指令时，可以使用分支指令中存储的符号位和进位位来恢复分支目标地址的高位。符号位和进位位可用于选择分支目标地址的三个可能的高位位组合之一。然后可以将所选择的高位比特值组合附加到分支目标地址的n-1个较低位，以形成完整的分支目标地址。

25. 发明授权

US08639943B2 Methods and systems for checking run-time integrity of secure code cross-reference to related applications 有权
标题翻译：用于检查安全代码的运行时完整性的方法和系统交叉引用到相关应用程序
公开(公告)号：US08639943B2
公开(公告)日：2014-01-28
申请号：US12485089
申请日：2009-06-16
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目是无效的，导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

26. 发明申请

US20110241423A1 Circuits, Systems and Methods to Detect and Accommodate Power Supply Voltage Droop 有权
标题翻译：检测和调节电源电压的电路，系统和方法Droop
公开(公告)号：US20110241423A1
公开(公告)日：2011-10-06
申请号：US12752515
申请日：2010-04-01
申请人： Jeffrey Todd Bridges , Sanjay B. Patel
发明人： Jeffrey Todd Bridges , Sanjay B. Patel
IPC分类号： H02J1/00
CPC分类号： G06F1/305 , Y10T307/406
摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.
摘要翻译：公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

27. 发明申请

US20110140752A1 Adaptive Clock Generators, Systems, and Methods 有权
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：US20110140752A1
公开(公告)日：2011-06-16
申请号：US12637321
申请日：2009-12-14
申请人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
发明人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

28. 发明授权

US07725625B2 Latency insensitive FIFO signaling protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US07725625B2
公开(公告)日：2010-05-25
申请号：US12179970
申请日：2008-07-25
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

29. 发明授权

US07568070B2 Instruction cache having fixed number of variable length instructions 有权
标题翻译：指令缓存具有固定数量的可变长度指令
公开(公告)号：US07568070B2
公开(公告)日：2009-07-28
申请号：US11193547
申请日：2005-07-29
申请人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
IPC分类号： G06F9/34
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/382
摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.
摘要翻译：固定数量的可变长度指令存储在指令高速缓存的每一行中。可变长度指令沿预定边界排列。由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

30. 发明授权

US07426626B2 TLB lock indicator 有权
标题翻译： TLB锁定指示灯
公开(公告)号：US07426626B2
公开(公告)日：2008-09-16
申请号：US11210526
申请日：2005-08-23
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/681
摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
摘要翻译：处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有的条目。响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

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