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21. 发明申请

US20110145512A1 Mechanisms To Accelerate Transactions Using Buffered Stores 有权
标题翻译：使用缓冲商店加速交易的机制
公开(公告)号：US20110145512A1
公开(公告)日：2011-06-16
申请号：US12638054
申请日：2009-12-15
申请人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。描述和要求保护其他实施例。

22. 发明申请

US20100332807A1 PERFORMING ESCAPE ACTIONS IN TRANSACTIONS 有权
标题翻译：执行交易中的避税行为
公开(公告)号：US20100332807A1
公开(公告)日：2010-12-30
申请号：US12493167
申请日：2009-06-26
申请人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
发明人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/467 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.
摘要翻译：在基于硬件的事务内存系统中执行非事务性转义操作。一种方法包括处理器上的硬件线程，开始针对线程的基于硬件的事务。所述方法还包括暂停所述基于硬件的事务并对所述线程执行非事务性的一个或多个操作，并且不受以下事务的影响：所述事务的事务监视和缓冲，所述事务的中止或者所述事务的中止提交交易。在对线程执行一个或多个操作之后，非事务性地，该方法还包括恢复事务并事务地执行附加操作。执行附加操作后，该方法还包括提交或中止事务。

23. 发明申请

US20100332768A1 FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS 审中-公开
标题翻译：灵活的读和写监视和缓冲存储块
公开(公告)号：US20100332768A1
公开(公告)日：2010-12-30
申请号：US12493162
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Vadim Bassin , Robert Y. Geva
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Vadim Bassin , Robert Y. Geva
IPC分类号： G06F12/08
CPC分类号： G06F11/362 , G06F12/0815
摘要： A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mechanism implementing an instruction set architecture including instructions accessible by software. The instructions are configured to: set per-hardware-thread, for a first thread, memory access monitoring indicators for a plurality of memory blocks, and test whether any monitoring indicator has been reset by the action of a conflicting memory access by another agent. The processor further includes mechanism configured to: detect conflicting memory accesses by other agents to the monitored memory blocks, and upon such detection of a conflicting access, reset access monitoring indicators corresponding to memory blocks having conflicting memory accesses, and remember that at least one monitoring indicator has been so reset.
摘要翻译：计算系统包括多个线程。计算系统被配置为允许监视和测试高速缓冲存储器中的存储器块以确定各种代理对存储器块的影响。该系统包括一个处理器。处理器包括实现包括可由软件访问的指令的指令集架构的机制。所述指令被配置为：针对第一线程设置每个硬件线程，用于多个存储器块的存储器访问监视指示符，以及通过另一代理器的冲突的存储器访问的动作来测试是否已经重置了任何监视指示符。所述处理器还包括被配置为：检测由所述被监视的存储器块的其他代理的冲突的存储器访问，并且在这种检测到冲突访问时，对应于具有冲突的存储器访问的存储器块的复位访问监视指示器，并且记住至少一个监视指示灯已经重置。

24. 发明授权

US08473921B2 Debugging mechanisms in a cache-based memory isolation system 有权
标题翻译：基于缓存的内存隔离系统中的调试机制
公开(公告)号：US08473921B2
公开(公告)日：2013-06-25
申请号：US12646438
申请日：2009-12-23
申请人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
发明人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
IPC分类号： G06F9/44
CPC分类号： G06F11/362 , G06F12/0817
摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
摘要翻译：在具有架构上重要的处理器高速缓存的系统中调试软件。可以在计算环境中实施一种方法。该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。该方法包括开始执行软件应用程序。在执行软件应用程序时运行调试器。软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

25. 发明授权

US08365016B2 Performing mode switching in an unbounded transactional memory (UTM) system 有权
标题翻译：在无界事务内存（UTM）系统中执行模式切换
公开(公告)号：US08365016B2
公开(公告)日：2013-01-29
申请号：US13307492
申请日：2011-11-30
申请人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
发明人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
IPC分类号： G06F11/00
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。描述和要求保护其他实施例。

26. 发明授权

US09092253B2 Instrumentation of hardware assisted transactional memory system 有权
标题翻译：硬件辅助事务记忆体系统的设计
公开(公告)号：US09092253B2
公开(公告)日：2015-07-28
申请号：US12638345
申请日：2009-12-15
申请人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
发明人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
IPC分类号： G06F9/44 , G06F9/46 , G06F11/36 , G06F11/34
CPC分类号： G06F9/467 , G06F11/3409 , G06F11/3466 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.
摘要翻译：监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

27. 发明授权

US08402218B2 Efficient garbage collection and exception handling in a hardware accelerated transactional memory system 有权
标题翻译：在硬件加速事务内存系统中高效的垃圾回收和异常处理
公开(公告)号：US08402218B2
公开(公告)日：2013-03-19
申请号：US12638929
申请日：2009-12-15
申请人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
发明人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/3834 , G06F9/467 , G06F12/0253 , G06F12/0815 , G06F12/082
摘要： Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.
摘要翻译：在硬件辅助交易中处理垃圾收集和异常。实施例在包括硬件辅助交易系统的计算环境中实现。实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此，异常对象出来的硬件辅助事务。

28. 发明授权

US08356166B2 Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers 有权
标题翻译：通过使用模式不可知事务读写障碍来最大限度地减少无界事务内存系统中的代码重复
公开(公告)号：US08356166B2
公开(公告)日：2013-01-15
申请号：US12493168
申请日：2009-06-26
申请人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3004 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3857 , G06F9/467
摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
摘要翻译：最大限度地减少无界事务内存系统中的代码重复。一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作与未来的TM实现可能会引入未知的未来TM执行模式。

29. 发明申请

US20110145798A1 DEBUGGING MECHANISMS IN A CACHE-BASED MEMORY ISOLATION SYSTEM 有权
标题翻译：基于缓存的内存分离系统中的调试机制
公开(公告)号：US20110145798A1
公开(公告)日：2011-06-16
申请号：US12646438
申请日：2009-12-23
申请人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
发明人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
IPC分类号： G06F9/44 , G06F15/76
CPC分类号： G06F11/362 , G06F12/0817
摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
摘要翻译：在具有架构上重要的处理器高速缓存的系统中调试软件。可以在计算环境中实施一种方法。该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。该方法包括开始执行软件应用程序。在执行软件应用程序时运行调试器。软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

30. 发明申请

US20110145304A1 EFFICIENT GARBAGE COLLECTION AND EXCEPTION HANDLING IN A HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：硬件加速传输存储系统中的高效收集和异常处理
公开(公告)号：US20110145304A1
公开(公告)日：2011-06-16
申请号：US12638929
申请日：2009-12-15
申请人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
发明人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
IPC分类号： G06F17/00 , G06F12/00 , G06F12/02
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/3834 , G06F9/467 , G06F12/0253 , G06F12/0815 , G06F12/082
摘要： Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.
摘要翻译：在硬件辅助交易中处理垃圾收集和异常。实施例在包括硬件辅助交易系统的计算环境中实现。实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此，异常对象出来的硬件辅助事务。

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