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21. 发明申请

US20150140697A1 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 有权
标题翻译：使用多模式图像处理的测试方法
公开(公告)号：US20150140697A1
公开(公告)日：2015-05-21
申请号：US14607160
申请日：2015-01-28
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Jin Cho , Hui Zang
IPC分类号： H01L21/66 , H01L21/8234
CPC分类号： H01L22/14 , G03F7/70466 , H01L21/823431 , H01L22/10 , H01L22/12 , H01L22/34
摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
摘要翻译：提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

22. 发明授权

US10622457B2 Forming replacement low-K spacer in tight pitch fin field effect transistors 有权
公开(公告)号：US10622457B2
公开(公告)日：2020-04-14
申请号：US14879968
申请日：2015-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC. , STMicroelectronics, Inc.
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165
CPC分类号： H01L29/6656 , H01L21/76829 , H01L21/76897 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41775 , H01L29/41791 , H01L29/6653 , H01L29/66515 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

23. 发明授权

US10622357B2 FinFET including tunable fin height and tunable fin width ratio 有权
公开(公告)号：US10622357B2
公开(公告)日：2020-04-14
申请号：US16294117
申请日：2019-03-06
申请人： International Business Machines Corporation , GlobalFoundries, Inc. , STMicroelectronics, Inc.
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/092 , H01L21/033 , H01L21/8238 , H01L29/16 , H01L29/78 , H01L29/06 , H01L21/308 , H01L21/84 , H01L27/12 , H01L29/10 , H01L29/165
CPC分类号： H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

24. 发明授权

US10395995B2 Dual liner silicide 有权
公开(公告)号：US10395995B2
公开(公告)日：2019-08-27
申请号：US15956082
申请日：2018-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417 , H01L29/08 , H01L29/45 , H01L23/522 , H01L21/768 , H01L21/285
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

25. 发明授权

US10217672B2 Vertical transistor devices with different effective gate lengths 有权
公开(公告)号：US10217672B2
公开(公告)日：2019-02-26
申请号：US15889654
申请日：2018-02-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Chun-Chen Yeh , Tenko Yamashita , Kangguo Cheng
IPC分类号： H01L27/00 , H01L29/00 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/78 , H01L29/423 , H01L21/306 , H01L21/308 , H01L21/8234 , H01L27/088
摘要： A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. A second vertical transistor device positioned above the semiconductor substrate includes a second gate structure, a second top spacer positioned above the second gate structure and having a second thickness in a vertical direction less than the first thickness, and a second doped top source/drain structure positioned above the second top spacer.

26. 发明授权

US10199480B2 Controlling self-aligned gate length in vertical transistor replacement gate flow 有权
公开(公告)号：US10199480B2
公开(公告)日：2019-02-05
申请号：US15280451
申请日：2016-09-29
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Tenko Yamashita , Kangguo Cheng , Chun-Chen Yeh
IPC分类号： H01L29/08 , H01L29/66 , H01L29/78 , H01L21/033 , H01L27/088 , H01L29/417
摘要： A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height. The method further includes forming a top source/drain layer over the vertical channel, replacing the dummy gate with a metal gate, and forming self-aligned source, drain and gate contacts.

27. 发明申请

US20180240715A1 METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS AND THE RESULTING DEVICES 审中-公开
公开(公告)号：US20180240715A1
公开(公告)日：2018-08-23
申请号：US15889654
申请日：2018-02-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Chun-Chen Yeh , Tenko Yamashita , Kangguo Cheng
IPC分类号： H01L21/8238 , H01L21/324 , H01L29/66 , H01L29/423 , H01L21/306 , H01L29/78 , H01L21/308 , H01L27/092
CPC分类号： H01L21/823885 , H01L21/30604 , H01L21/3085 , H01L21/823418 , H01L21/823468 , H01L21/823487 , H01L21/823814 , H01L21/82385 , H01L21/823864 , H01L27/088 , H01L27/092 , H01L29/42376 , H01L29/6656 , H01L29/66666 , H01L29/7827
摘要： A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. A second vertical transistor device positioned above the semiconductor substrate includes a second gate structure, a second top spacer positioned above the second gate structure and having a second thickness in a vertical direction less than the first thickness, and a second doped top source/drain structure positioned above the second top spacer.

28. 发明申请

US20180233417A1 DUAL LINER SILICIDE 审中-公开
公开(公告)号：US20180233417A1
公开(公告)日：2018-08-16
申请号：US15956082
申请日：2018-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/45 , H01L29/417 , H01L29/08 , H01L27/092 , H01L23/522 , H01L21/768 , H01L21/285
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

29. 发明授权

US09991366B2 Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET 有权
公开(公告)号：US09991366B2
公开(公告)日：2018-06-05
申请号：US15092039
申请日：2016-04-06
申请人： GLOBALFOUNDRIES INC.
发明人： Veeraraghavan S. Basker , Krishna Iyengar , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/165 , H01L29/04 , H01L29/08
CPC分类号： H01L29/66795 , H01L29/045 , H01L29/0847 , H01L29/165 , H01L29/7848 , H01L29/785
摘要： After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

30. 发明申请

US20180122711A1 DUAL LINER SILICIDE 审中-公开
公开(公告)号：US20180122711A1
公开(公告)日：2018-05-03
申请号：US15847028
申请日：2017-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/08 , H01L21/768
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

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