专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20150242317A1 MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD 审中-公开
标题翻译：多核处理器系统，控制程序和控制方法
公开(公告)号：US20150242317A1
公开(公告)日：2015-08-27
申请号：US14710138
申请日：2015-05-12
申请人： FUJITSU LIMITED
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/544 , G06F12/00 , G06F12/0808 , G06F12/0833 , G06F12/0842 , G06F12/1072 , G06F2212/1016 , G06F2212/1044 , G06F2212/283
摘要： A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
摘要翻译：多核处理器系统包括：存储单元，对于被定义为输入给定数据的线程的每个输入目标线程，存储用于输入目的线程的分配目的地核心的识别信息; 以及被配置为在存储器单元中更新并且当检测到输入目的地线程被分配到多核处理器时的多核处理器，用于输入目的地线程的分配目的地核心的识别信息; 检测给定数据的写入请求; 基于检测到写入请求的给定数据识别存储在存储单元中的信息之间的更新的标识信息; 并将给定数据存储在更新的识别信息中指定的分配目的地核心的存储器中，以及构成多核处理器的核心。

22. 发明授权

US09069756B2 Data transfer control apparatus, data transfer control method, and computer product 有权
公开(公告)号：US09069756B2
公开(公告)日：2015-06-30
申请号：US13718302
申请日：2012-12-18
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

23. 发明申请

US20150177361A1 DETERMINING METHOD, COMPUTER PRODUCT, DETERMINING APPARATUS, AND DETERMINING SYSTEM 有权
标题翻译：测定方法，计算机产品，测定装置和测定系统
公开(公告)号：US20150177361A1
公开(公告)日：2015-06-25
申请号：US14636731
申请日：2015-03-03
申请人： FUJITSU LIMITED
发明人： Toshiya OTOMO , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Yuta Teranishi
IPC分类号： G01S5/02 , H04W4/02
CPC分类号： G01S5/0289 , H04W4/02 , H04W4/023 , H04W84/18
摘要： A determining method includes obtaining by each monitoring apparatus among plural monitoring apparatuses disposed encompassing a given area having plural wireless communications apparatuses, hop count information that indicates a hop count of a wireless signal transmitted by one wireless communications apparatus among the wireless communications apparatuses and received by the monitoring apparatus via multi-hop communication by the wireless communications apparatuses; calculating by each monitoring apparatus, an estimated line that represents candidates of a position of the one wireless communications apparatus, the estimated line being calculated from an estimated distance between the monitoring apparatus and the one wireless communications apparatus, based on the hop count; correcting by each monitoring apparatus, the calculated estimated line based on information indicating a node-less area in which no wireless communications apparatus of the given area is present; and determining the position of the one wireless communications apparatus based on intersections of the corrected estimated lines.
摘要翻译：一种确定方法，包括：通过各监视装置获取多个监视装置，包括具有多个无线通信装置的给定区域的多个监视装置，指示由无线通信装置中的一个无线通信装置发送的无线信号的跳数的跳数计数信息，并由所述监视装置经由所述无线通信装置的多跳通信; 由所述监视装置计算表示所述一个无线通信装置的位置的候选的估计线，根据所述跳数，从所述监视装置与所述一个无线通信装置之间的估计距离算出所述估计线; 通过每个监视装置校正基于指示不存在给定区域的无线通信装置的无节点区域的信息的所计算的估计线; 以及基于所述校正的估计线的交点来确定所述一个无线通信装置的位置。

24. 发明申请

US20150169456A1 MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT 有权
标题翻译：多核处理器系统，高速缓存控制方法和计算机产品
公开(公告)号：US20150169456A1
公开(公告)日：2015-06-18
申请号：US14630400
申请日：2015-02-24
申请人： FUJITSU LIMITED
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/1028 , G06F2212/171 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要： A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
摘要翻译：多核处理器系统包括处理器，其被配置为建立存储在由多个核存取的高速缓冲存储器中的共享数据值的一致性; 检测由所述核心中的第一核心执行的第一线程; 在检测到第一线程时识别，第二线程由除第一核心之外的核心和核心之中的第二核心执行; 确定是否存在由第一线程和第二线程共同访问的共享数据; 并且在确定不存在共同访问的共享数据时，停止对应于第一核心的第一高速缓存存储器和对应于第二核心的第二高速缓存存储器的一致性建立。

25. 发明授权

US08996811B2 Scheduler, multi-core processor system, and scheduling method 有权
标题翻译：调度器，多核处理器系统和调度方法
公开(公告)号：US08996811B2
公开(公告)日：2015-03-31
申请号：US13749606
申请日：2013-01-24
申请人： Fujitsu Limited
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F12/08 , G06F9/48 , B29D22/00 , B29C49/06 , B29C49/42 , B29C49/18 , B29C49/64
CPC分类号： G06F12/0811 , B29C49/062 , B29C49/18 , B29C49/4215 , B29C49/6427 , B29D22/003 , G06F9/544 , G06F12/0875 , G06F12/0888 , G06F2212/283
摘要： A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
摘要翻译：一种调度器，其使多核处理器中的给定核心确定要由所述多核处理器的核心执行的进程的优先级是否大于或等于阈值; 存储到执行具有大于或等于阈值的优先级的处理的每个核心的高速缓冲存储器，由执行时的进程访问的数据; 存储到与高速缓冲存储器不同的存储区域，并且哪个访问相对较慢，由具有不大于或等于阈值的优先级的进程访问的数据; 并且当所请求的核心发出存储在存储器区域中的数据的访问请求时，将保存在存储器区域中的数据保存到请求核心的高速缓冲存储器。

26. 发明申请

US20140082637A1 DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理方法和数据处理系统
公开(公告)号：US20140082637A1
公开(公告)日：2014-03-20
申请号：US14085141
申请日：2013-11-20
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/54
CPC分类号： G06F9/542 , G06F9/528
摘要： A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.
摘要翻译：一种由第一数据处理装置执行的数据处理方法，包括响应于第一处理的处理请求而获取关于第一处理的处理信息; 设置关于第一处理的处理信息中包括的表示“真”的第一处理标志; 在执行第一处理之后，设置关于第一处理的处理信息的第一结束标志以指示“真”; 获取关于在第一处理之后执行的第三处理之前要执行的第二处理的处理信息; 以及基于包括在关于第二处理的处理信息中的第二处理标志和第二结束标志来确定要执行的处理。

27. 发明申请

US20140026143A1 EXCLUSIVE ACCESS CONTROL METHOD AND COMPUTER PRODUCT 有权
标题翻译：独家访问控制方法和计算机产品
公开(公告)号：US20140026143A1
公开(公告)日：2014-01-23
申请号：US14036272
申请日：2013-09-25
申请人： Fujitsu Limited
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F9/526 , G06F12/00
摘要： An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts.
摘要翻译：排他访问控制方法由具有操作系统的计算机执行，当被排除的线程访问共享资源时，执行禁止排除的线程尝试访问共享资源的第一独占访问控制处理，直到排他访问控制被释放，独占访问控制过程正在根据所排除的线程尝试次数执行以访问共享资源。独占访问控制方法包括：当第一线程执行允许排除的第二独占访问控制过程时，至少包括被排除的线程并且与第一线程不同的第二线程的计数，访问共享资源的尝试次数线程尝试访问共享资源，直到被排除的线程被允许访问; 并且通过第二线程将计数的尝试次数存储到存储器区域。

28. 发明申请

US20130198390A1 COMPUTER PRODUCT, TERMINAL, SERVER, DATA SHARING METHOD, AND DATA DISTRIBUTION METHOD 有权
标题翻译：计算机产品，终端，服务器，数据共享方法和数据分配方法
公开(公告)号：US20130198390A1
公开(公告)日：2013-08-01
申请号：US13801433
申请日：2013-03-13
申请人： Fujitsu Limited
发明人： Koji KURIHARA , Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki
IPC分类号： H04L12/56
CPC分类号： H04L47/70 , G06F17/30283
摘要： A computer-readable recording medium stores a data sharing program that causes a processor of a first terminal to execute a process that includes detecting a communication bandwidth used between the first terminal and a second terminal that are communicably connected in an ad-hoc network; comparing the detected communication bandwidth and a bandwidth related to a storage apparatus of the first terminal; determining an operation scheme related to data sharing of data in the storage apparatus of the first terminal and data in a storage apparatus of the second terminal, based on a comparison result obtained at the comparing; notifying the second terminal of the determined operation scheme; and executing a mounting process that enables access of the storage apparatus of the first terminal by the second terminal, based on the determined operation scheme.
摘要翻译：计算机可读记录介质存储数据共享程序，其使得第一终端的处理器执行包括检测在第一终端和第二终端之间使用的通信带宽的处理，所述通信带宽可通信地连接在自组织网络中; 比较检测到的通信带宽和与第一终端的存储装置有关的带宽; 基于在比较时获得的比较结果，确定与第一终端的存储装置中的数据的数据共享相关的操作方案和第二终端的存储装置中的数据; 通知所述第二终端所确定的操作方案; 以及基于所确定的操作方案执行能够由第二终端访问第一终端的存储装置的安装处理。

29. 发明申请

US20130124804A1 DATA RESTORATION PROGRAM, DATA RESTORATION APPARATUS, AND DATA RESTORATION METHOD 有权
标题翻译：数据恢复程序，数据恢复装置和数据恢复方法
公开(公告)号：US20130124804A1
公开(公告)日：2013-05-16
申请号：US13730514
申请日：2012-12-28
申请人： Fujitsu Limited
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F12/00
CPC分类号： G06F1/30 , G06F11/1004 , G06F11/1076 , G06F12/0646 , G06F12/0804 , G06F2211/1059 , G06F2212/1028 , G06F2212/254
摘要： A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.
摘要翻译：计算机可读记录介质存储使能够访问配备有易失性存储器的多核处理器和访问易失性存储器的多个核的计算机执行数据恢复处理的程序。所述数据恢复处理包括检测对所述多核处理器中的任一核的挂起指令; 并且当检测到所述暂停指令时，恢复存储在由接收到所述挂起指令的核心访问的易失性存储器中的数据，所述数据被恢复在由所述核操作的存储器访问的共享存储器中，并且基于存储在所访问的所述易失性存储器中的奇偶校验数据由核心在核心以外的核心接收暂停指令。

30. 发明申请

US20130097384A1 MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT 有权
公开(公告)号：US20130097384A1
公开(公告)日：2013-04-18
申请号：US13712816
申请日：2012-12-12
申请人： FUJITSU LIMITED
发明人： Takahisa SUZUKI , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/1028 , G06F2212/171 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要： A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式