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21. 发明申请

US20060152249A1 Configuration circuit for programmable logic devices 有权
标题翻译：可编程逻辑器件的配置电路
公开(公告)号：US20060152249A1
公开(公告)日：2006-07-13
申请号：US11357145
申请日：2006-02-21
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173 , H03K19/0175 , G06F7/38
CPC分类号： H03K19/177 , H03K19/017509 , H03K19/17764
摘要： A configuration circuit, comprising: a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to said output; wherein, the voltage conversion circuit generates a configurable control signal either at the ground voltage level or the second voltage level by configuring the storage element.
摘要翻译：一种配置电路，包括：耦合在接地电压和第一电压之间的可配置存储元件，所述存储元件产生输出; 以及电压转换电路，其耦合在所述接地电压和比所述第一电压低的电平处的第二电压，所述电路还耦合到所述输出; 其中，所述电压转换电路通过配置所述存储元件来产生处于地电压或第二电压电平的可配置控制信号。

22. 发明申请

US20050162933A1 Programmable interconnect structures 有权
标题翻译：可编程互连结构
公开(公告)号：US20050162933A1
公开(公告)日：2005-07-28
申请号：US11040731
申请日：2005-01-24
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G06F7/38 , G06F17/50 , G11C5/00 , H03K17/693 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable multiplexer comprising: a plurality of inputs and an output, wherein the inputs are coupled to said plurality of wires, and the output is coupled to said input of the buffer; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select one of said plurality of wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and a plurality of outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said plurality of wires; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select said buffer output to couple to one of said plurality of wires; wherein, a signal received by the buffer on any one of the plurality of wires is buffered and transmitted to one or more of the other wires. The area of the structure is significantly reduced by increasing the number of programmable switches, generating a layout efficient wire sharing multiplexing scheme, moving the memory elements to a vertical position and using a single large area output stage in the buffer.
摘要翻译：一种集成电路中的可编程互连结构，包括：多条导线; 以及包括输入和输出的缓冲器，所述缓冲器在输入处接收弱信号并在输出端提供缓冲信号; 以及第一可编程多路复用器，包括：多个输入和输出，其中所述输入耦合到所述多条导线，并且所述输出耦合到所述缓冲器的所述输入; 以及包括多个存储器元件的用户可配置配置电路，其中存储在所述存储器元件中的数据选择所述多条线中的一条以耦合到所述缓冲器输入; 以及第二可编程多路复用器，包括：输入和多个输出，其中所述输入耦合到所述缓冲器的所述输出，并且所述输出耦合到所述多条导线; 以及包括多个存储器元件的用户可配置配置电路，其中存储在所述存储器元件中的数据选择所述缓冲器输出以耦合到所述多条线中的一条; 其中，所述缓冲器在所述多个导线中的任何一个上接收的信号被缓冲并传输到一个或多个其它导线。通过增加可编程开关的数量，生成布局高效的有线共享复用方案，将存储元件移动到垂直位置，并在缓冲器中使用单个大面积输出级，可显着减少结构的面积。

23. 发明申请

US20050121721A1 Insulated-gate field-effect thin film transistors 有权
标题翻译：绝缘栅场效应薄膜晶体管
公开(公告)号：US20050121721A1
公开(公告)日：2005-06-09
申请号：US10979024
申请日：2004-11-02
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H01L21/00 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/74 , H01L29/786
CPC分类号： H01L27/1214 , H01L21/26513 , H01L21/2658 , H01L27/0688 , H01L27/1203 , H01L29/665 , H01L29/78621 , H01L29/78696
摘要： A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer, said gate region receiving a gate voltage comprised of: a first level that modulate said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said thin film layer in the channel region; and a second level that modulate said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate surface of the thin film layer in said channel region.
摘要翻译：公开了一种新的绝缘栅场效应薄膜晶体管（Gated-FET）。一种半导体薄膜栅极FET器件，包括：形成在半导体薄膜层上的轻掺杂电阻沟道区，所述沟道的厚度包括整个薄膜厚度; 以及沉积在所述沟道表面上的绝缘体层，所述栅极区域形成在沉积在所述绝缘体层上的栅极材料上，所述栅极区域接收栅极电压，所述栅极电压包括：第一电平，其将所述沟道电阻调制到基本上不导通的状态，在沟道区域中从所述薄膜层中充分耗尽多数载流子; 以及第二电平，其通过在所述沟道区域中至少部分地积聚靠近所述薄膜层的栅极表面的多数载流子来将所述沟道电阻调制到基本导电状态。

24. 发明申请

US20050091630A1 Programmable interconnect structures 有权
标题翻译：可编程互连结构
公开(公告)号：US20050091630A1
公开(公告)日：2005-04-28
申请号：US10691013
申请日：2003-10-23
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G06F7/38 , G06F17/50 , G11C5/00 , H03K17/693 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits. A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and fabricating an interconnect and routing layer substantially above said memory circuits to connect said pass-gates and one of said memory circuits and conductive pattern.
摘要翻译：用于集成电路的可编程互连结构包括：制造在衬底层上以将第一节点电连接到第二节点的通过门; 以及配置电路，其包括至少一个存储元件，以控制基本上在所述衬底层上方制造的所述通孔; 以及可编程方法，用于在隔离所述第一和第二节点之间选择并连接所述第一和第二节点。一种用于集成电路的可编程缓冲器结构包括：第一和第二端子; 以及耦合在所述第一和第二端子之间的可编程上拉和可编程下拉电路; 以及配置电路，包括耦合到所述上拉和下拉电路的至少一个存储元件; 以及可编程方法，用于通过停用所述上拉和下拉电路来将所述第一端子与第二端子隔离，并且通过激活所述上拉和下拉电路将所述第一端子耦合到第二端子来进行选择。形成用于集成电路的可编程互连结构的方法包括：在衬底层上制造一个或多个栅极以电连接两个点; 并且选择性地制造基本上在所述通过栅极上方的存储器电路或导电图案以控制所述通孔的一部分; 以及基本上在所述存储器电路之上制造互连和布线层，以连接所述通孔和所述存储器电路和导电图案之一。

25. 发明授权

US5949250A Two-terminal electrically-reprogrammable programmable logic element 失效
公开(公告)号：US5949250A
公开(公告)日：1999-09-07
申请号：US104015
申请日：1998-06-24
申请人： Dominik Schmidt , Raminda Madurawe
发明人： Dominik Schmidt , Raminda Madurawe
IPC分类号： G11C16/04 , G11C16/10 , G11C16/14 , H01L29/423 , H01L29/788 , H03K19/173
CPC分类号： H01L29/7883 , G11C16/0416 , G11C16/10 , G11C16/14 , H01L29/42324
摘要： A non-volatile two terminal programmable logic element and associated methods for charging and discharging are disclosed. The logic element includes one input and one output terminal, a first capacitor region, a second capacitor region, and a floating gate (transistor-type) structure. The first capacitor region does not permit tunneling. The second capacitor region permits tunneling between its respective electrodes when a predetermined voltage, substantially higher than the normal operating voltage is applied. The source is connected to the input terminal and one electrode of the first capacitor region. The drain is connected to the output terminal and one electrode of the second capacitor region. The floating gate is connected to the other electrodes of the first and second capacitor regions. A programmable logic device constructed from these elements and associated methods of programming and erasing such a device are also shown.

26. 发明申请

US20090243652A1 INCREMENTER BASED ON CARRY CHAIN COMPRESSION 有权
标题翻译：基于携带链压缩的增量仪
公开(公告)号：US20090243652A1
公开(公告)日：2009-10-01
申请号：US12480213
申请日：2009-06-08
申请人： Nij Dorairaj , Raminda Madurawe
发明人： Nij Dorairaj , Raminda Madurawe
IPC分类号： H03K19/173 , G06F7/50
CPC分类号： H03K19/17728 , G11C7/1006 , G11C11/419 , G11C2207/102
摘要： A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.
摘要翻译：公开了一种用于递增或减少n位数据的计算单元。该单元具有用于处理n位数据的n / 3个逻辑块，每个逻辑块包括：第一和第二多路复用器，用于传播进位链; 以及耦合到多路复用器的进位链的第一，第二和第三异或（XOR）电路，以产生3位递增的输出。

27. 发明申请

US20080074146A1 Three dimensional integrated circuits 有权
标题翻译：三维集成电路
公开(公告)号：US20080074146A1
公开(公告)日：2008-03-27
申请号：US11985822
申请日：2007-11-19
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/17724 , H01L21/8221 , H01L27/0688 , H03K19/1735 , H03K19/177 , H03K19/17736 , H03K19/17748 , H03K19/17796
摘要： A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.
摘要翻译：一种可编程集成电路（IC），其中：可编程逻辑电路通过配置由基本上位于晶体管上方或下方的只读存储器（ROM）元件产生的晶体管栅极控制信号而被编程为用户指定。

28. 发明申请

US20080067594A1 Insulated-gate field-effect thin film transistors 审中-公开
标题翻译：绝缘栅场效应薄膜晶体管
公开(公告)号：US20080067594A1
公开(公告)日：2008-03-20
申请号：US11985829
申请日：2007-11-19
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H01L29/786
CPC分类号： H01L27/1214 , H01L21/26513 , H01L21/2658 , H01L27/0688 , H01L27/1203 , H01L29/665 , H01L29/78621 , H01L29/78696
摘要： A semiconductor thin film Gated-FET device, comprising: a resistive thin film channel region positioned between a source and a drain region, said channel region comprising a lower level of said source and drain majority carrier type; and a gate region coupled to the channel region by a dielectric region, wherein a first gate voltage modulates the channel resistance to a substantially non-conductive state by fully depleting majority carriers from the thin film channel region. Said device, wherein a second gate voltage modulates the channel resistance to a substantially conductive state by leaving adequate majority carriers in the thin film layer channel region.
摘要翻译：一种半导体薄膜栅极FET器件，包括：位于源极和漏极区域之间的电阻薄膜沟道区，所述沟道区包括较低级的所述源极和漏极多数载流子型; 以及通过电介质区域耦合到沟道区域的栅极区域，其中第一栅极电压通过从薄膜沟道区域充分耗尽多数载流子将沟道电阻调制到基本上非导通状态。所述器件，其中第二栅极电压通过在薄膜层沟道区域中留下足够多的载流子来将沟道电阻调制到基本上导电的状态。

29. 发明申请

US20070210830A1 Three dimensional integrated circuits 有权
标题翻译：三维集成电路
公开(公告)号：US20070210830A1
公开(公告)日：2007-09-13
申请号：US11801739
申请日：2007-05-11
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/17724 , H01L21/8221 , H01L27/0688 , H03K19/1735 , H03K19/177 , H03K19/17736 , H03K19/17748 , H03K19/17796
摘要： In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.
摘要翻译：在第一方面，一种三维半导体器件，其中：耦合到可编程逻辑电路以对所述逻辑电路进行编程的可配置存储器元件位于所述逻辑电路之上。在第二方面中，一种三维半导体器件，包括：具有电路块的第一模块层; 以及基本上位于第一模块层上方的第二模块层，包括耦合到电路块的配置电路以对电路块进行编程。

30. 发明申请

US20070210336A1 Semiconductor devices fabricated with different processing options 有权
标题翻译：采用不同加工方式制造的半导体器件
公开(公告)号：US20070210336A1
公开(公告)日：2007-09-13
申请号：US11801738
申请日：2007-05-11
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H01L27/10
CPC分类号： G06F17/5054 , G06F17/5045 , G06F17/5077 , G06F2217/06 , G11C16/0433 , G11C17/16 , H01L27/1052 , H03K19/17796
摘要： A semiconductor device, wherein: a first fabricating option provides a plurality of user configurations to configure the device functionality; and a second fabricating option hard-wires a said functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to the first option.
摘要翻译：一种半导体器件，其中：第一制造选项提供多个用户配置以配置所述设备功能; 以及第二制造选项硬连接所述功能配置，所述第二选项包括多个公共掩模和与第一选项相比较少的处理步骤。

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