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21. 发明申请

US20110145459A1 ELECTRONIC POWER MANAGEMENT SYSTEM 有权
标题翻译：电子电源管理系统
公开(公告)号：US20110145459A1
公开(公告)日：2011-06-16
申请号：US13028440
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
摘要翻译：一种电子电源管理系统，包括可在不同安全性和上下文相关模式下操作的多个处理器，并且具有相应的电源电压输入和时钟输入，所述处理器具有至少一个中断输入和至少一个等待中断输出。该系统还包括功率控制电路，其可操作以可配置地调节所述电源电压输入和时钟输入的电源电压和时钟速率。所述系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器中的至少一个可操作以响应于所述中断信号配置所述功率控制电路。

22. 发明申请

US20090049220A1 INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES 有权
标题翻译：中断相关电路，系统和过程
公开(公告)号：US20090049220A1
公开(公告)日：2009-02-19
申请号：US12100534
申请日：2008-04-10
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit (4234A) having plural interrupt-related output lines (4245) and selectively operable in response to an interrupt-related signal on said interrupt-related input line (4235) depending on an active or inactive status of each of said security-related status input line (4236) and said context-related status input line (4237).
摘要翻译：电子中断电路包括中断相关输入线（4235），安全相关状态输入线（4236），上下文相关状态输入线（4237）和具有多个中断相关输出的转换电路（4234A）线路（4245），并且根据所述安全相关状态输入线路（4236）和所述上下文相关的每个的活动或不活动状态，响应于所述中断相关输入线路（4235）上的中断相关信号选择性地操作状态输入线（4237）。

23. 发明申请

US20110173363A1 PROCESSOR SYSTEM WITH AN APPLICATION AND A MAINTENANCE FUNCTION 有权
标题翻译：具有应用和维护功能的处理器系统
公开(公告)号：US20110173363A1
公开(公告)日：2011-07-14
申请号：US13028459
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
摘要翻译：具有应用程序和维护功能的处理器系统，如果同时执行则会干扰应用程序。处理器系统包括可在不同安全性和上下文相关模式下操作的一组处理器核心，所述处理器具有至少一个中断输入和至少一个等待中断输出。所述处理器系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器核中的至少一个可响应于所述中断信号而可操作以调度在时间上分离的维护功能执行应用程序。

24. 发明授权

US07934036B2 Interrupt-related circuits, systems, and processes 有权
标题翻译：中断相关电路，系统和过程
公开(公告)号：US07934036B2
公开(公告)日：2011-04-26
申请号：US12100534
申请日：2008-04-10
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.
摘要翻译：电子中断电路包括中断相关输入线，安全相关状态输入线，上下文相关状态输入线和具有多个中断相关输出线的转换电路，并且可响应于中断相关信号选择性地工作在所述中断相关输入线上，取决于所述安全相关状态输入线和所述上下文相关状态输入线中的每一个的活动状态或不活动状态。

25. 发明授权

US07890753B2 Secure mode for processors supporting MMU and interrupts 有权
标题翻译：支持MMU和中断的处理器的安全模式
公开(公告)号：US07890753B2
公开(公告)日：2011-02-15
申请号：US10256642
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： H04L29/06
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓存，写入缓冲器和存储器管理单元的处理器系统上，数字系统被提供有以非侵入式方式内置的安全模式（第三级特权）。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

26. 发明授权

US07237081B2 Secure mode for processors supporting interrupts 有权
标题翻译：支持中断的处理器的安全模式
公开(公告)号：US07237081B2
公开(公告)日：2007-06-26
申请号：US10256523
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： G06F12/14 , G06F11/30 , G06F12/00 , H04L9/32 , H04L9/00
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓冲存储器，写入缓冲器和写入缓冲器的处理器系统中，数字系统被提供有以非侵入式方式构建的安全模式（3级的特权级别）内存管理单元。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

27. 发明授权

US06989702B2 Retention register with normal functionality independent of retention power supply 有权
标题翻译：保持寄存器具有正常功能，独立于保持电源
公开(公告)号：US06989702B2
公开(公告)日：2006-01-24
申请号：US10613271
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C14/00
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的阳极（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

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