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21. 发明申请

US20060159104A1 QUEUEING SYSTEM FOR PROCESSORS IN PACKET ROUTING OPERATIONS 有权
标题翻译：分组路由操作中处理器的队列系统
公开(公告)号：US20060159104A1
公开(公告)日：2006-07-20
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，在处理期间用于分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

22. 发明申请

US20060153197A1 Queueing system for processors in packet routing operations 有权
公开(公告)号：US20060153197A1
公开(公告)日：2006-07-13
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

23. 发明授权

US07058064B2 Queueing system for processors in packet routing operations 有权
公开(公告)号：US07058064B2
公开(公告)日：2006-06-06
申请号：US09737375
申请日：2000-12-14
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

24. 发明授权

US07551626B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07551626B2
公开(公告)日：2009-06-23
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F3/00 , G06F13/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

25. 发明申请

US20070294702A1 METHOD AND APPARATUS FOR IMPLEMENTING ATOMICITY OF MEMORY OPERATIONS IN DYNAMIC MULTI-STREAMING PROCESSORS 有权
标题翻译：在动态多流程处理器中实现存储器操作原理的方法和装置
公开(公告)号：US20070294702A1
公开(公告)日：2007-12-20
申请号：US11676541
申请日：2007-02-20
申请人： Stephen Melvin , Mario Nemirovsky
发明人： Stephen Melvin , Mario Nemirovsky
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源，以及用于锁定由处理器的流共享的所选择的存储器位置的锁定机构，硬件锁定机构操作在原子存储器序列启动时设置锁定，并且当原子存储器序列完成时清除锁定。在优选实施例中，锁定机构包括与处理器的每个流相关联的一个或多个存储位置，每个存储位置能够存储存储器地址锁定位和失速位。还教导了使用该装置实施本发明的方法。

26. 发明申请

US20120173762A1 METHOD FOR INPUT OUTPUT EXPANSION IN AN EMBEDDED SYSTEM UTILIZING CONTROLLED TRANSITIONS OF FIRST AND SECOND SIGNALS 有权
标题翻译：使用第一和第二信号控制过渡的嵌入式系统中的输入输出扩展方法
公开(公告)号：US20120173762A1
公开(公告)日：2012-07-05
申请号：US13412341
申请日：2012-03-05
申请人： Stephen Melvin
发明人： Stephen Melvin
IPC分类号： G06F3/00
CPC分类号： G06F13/4208
摘要： A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.
摘要翻译：描述了一种用于扩展嵌入式系统中的输入/输出的方法，其中不需要来自主机控制器的附加选通或使能线。通过在控制两个现有数据或选择线时以特定方式控制信号电平的转变，扩展输入和/或输出装置可在内部产生选通和/或使能信号。然后，该内部选通和/或使能信号用于存储输出数据或使能输入数据。主机控制器通常利用软件或固件来控制数据转换，但不需要额外的电线，并且不需要对现有外围设备进行任何改变。因此，当没有可用的附加控制线和现有信号中的未使用状态时，可以扩展现有系统。

27. 发明申请

US20100023648A1 METHOD FOR INPUT OUTPUT EXPANSION IN AN EMBEDDED SYSTEM UTILIZING CONTROLLED TRANSITIONS OF FIRST AND SECOND SIGNALS 有权
标题翻译：使用第一和第二信号控制过渡的嵌入式系统中的输入输出扩展方法
公开(公告)号：US20100023648A1
公开(公告)日：2010-01-28
申请号：US12573777
申请日：2009-10-05
申请人： Stephen Melvin
发明人： Stephen Melvin
IPC分类号： G06F3/00
CPC分类号： G06F13/4208
摘要： A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.
摘要翻译：描述了一种用于扩展嵌入式系统中的输入/输出的方法，其中不需要来自主机控制器的附加选通或使能线。通过在控制两个现有数据或选择线时以特定方式控制信号电平的转变，扩展输入和/或输出装置可在内部产生选通和/或使能信号。然后，该内部选通和/或使能信号用于存储输出数据或使能输入数据。主机控制器通常利用软件或固件来控制数据转换，但不需要额外的电线，并且不需要对现有外围设备进行任何改变。因此，当没有可用的附加控制线和现有信号中的未使用状态时，可以扩展现有系统。

28. 发明申请

US20050267997A1 APPARATUS FOR INPUT/OUTPUT EXPANSION WITHOUT ADDITIONAL CONTROL LINES 有权
标题翻译：用于输入/输出扩展的设备，无附加控制线
公开(公告)号：US20050267997A1
公开(公告)日：2005-12-01
申请号：US10709084
申请日：2004-04-12
申请人： Stephen Melvin
发明人： Stephen Melvin
IPC分类号： G06F3/00 , G06F13/42
CPC分类号： G06F13/4208
摘要： An apparatus for expanding I/O is described in which no additional strobes or enable lines are necessary from the host controller. By sequencing data in a specific way when output to two existing data or select lines, an expansion I/O device can generate a strobe or enable signal internally. This internal strobe or enable signal is then used to store output data or enable input data. The host controller needs software or firmware to perform the data sequencing, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.
摘要翻译：描述了用于扩展I / O的装置，其中不需要来自主机控制器的附加选通或使能线。通过在输出到两个现有数据或选择行时以特定方式排序数据，扩展I / O设备可以在内部产生选通或使能信号。该内部选通或使能信号用于存储输出数据或使能输入数据。主机控制器需要软件或固件来执行数据排序，但不需要额外的电线，并且不需要对现有外围设备进行任何更改。因此，当没有可用的附加控制线和现有信号中的未使用状态时，可以扩展现有系统。

29. 发明授权

US08812875B1 Virtual self-destruction of stored information 有权
标题翻译：存储信息的虚拟自毁
公开(公告)号：US08812875B1
公开(公告)日：2014-08-19
申请号：US12758475
申请日：2010-04-12
申请人： Stephen Melvin
发明人： Stephen Melvin
IPC分类号： H04L9/00 , G06F21/00 , H04L9/08 , G06F21/78
CPC分类号： G06F21/88 , G06F21/602 , G06F21/6245 , G06F21/78 , G06F2221/2143 , G06F2221/2153 , H04L9/0891 , H04L9/0897
摘要： A method and apparatus are utilized to conveniently and swiftly render stored information inaccessible. Sensitive information is stored in an encrypted form and by eliminating the key or keys which are needed for decryption, the stored information becomes virtually destroyed. A variety of mechanisms and policies can be used to manage, set and eliminate decryption keys. In some cases decryption keys can be stored in volatile storage elements so that by merely interrupting power to the storage element, the decryption keys are eliminated. In this way, a manually controlled mechanism can be used to allow a user to accomplish a “self-destruct” of the stored information instantly without the need for the operation of any processor and without the need to change any stored information.
摘要翻译：使用方法和装置来方便地并且迅速地使存储的信息不可访问。敏感信息以加密形式存储，并且通过消除解密所需的密钥或密钥，所存储的信息被虚拟地销毁。可以使用各种机制和策略来管理，设置和消除解密密钥。在一些情况下，解密密钥可以存储在易失性存储元件中，从而仅通过中断对存储元件的电力，消除了解密密钥。以这种方式，可以使用手动控制的机制来允许用户立即完成所存储信息的“自毁”，而不需要任何处理器的操作，而不需要改变任何存储的信息。

30. 发明授权

US07650605B2 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors 有权
标题翻译：用于在动态多流处理器中实现存储器操作的原子性的方法和装置
公开(公告)号：US07650605B2
公开(公告)日：2010-01-19
申请号：US11676541
申请日：2007-02-20
申请人： Stephen Melvin , Mario D. Nemirovsky
发明人： Stephen Melvin , Mario D. Nemirovsky
IPC分类号： G06F9/00 , G06F7/38 , G06F13/28 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源，以及用于锁定由处理器的流共享的所选择的存储器位置的锁定机构，硬件锁定机构操作在原子存储器序列启动时设置锁定，并且当原子存储器序列完成时清除锁定。在优选实施例中，锁定机构包括与处理器的每个流相关联的一个或多个存储位置，每个存储位置能够存储存储器地址锁定位和失速位。还教导了使用该装置实施本发明的方法。

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