专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07358148B2 Adjustable self-aligned air gap dielectric for low capacitance wiring 有权
标题翻译：可调式自对准气隙电介质用于低电容布线
公开(公告)号：US07358148B2
公开(公告)日：2008-04-15
申请号：US11418921
申请日：2006-05-05
申请人： Robert M. Geffken , William T. Motsiff
发明人： Robert M. Geffken , William T. Motsiff
IPC分类号： H01L21/76
CPC分类号： H01L21/76831 , H01L21/76811 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.
摘要翻译：可调整的自对准低电容集成电路气隙结构包括邻近互连层上的第二互连的第一互连，沿着第一和第二互连的相邻侧形成的隔离物，以及形成在第一和第二互连之间的气隙。空气间隙在第一和第二互连中的至少一个的上表面上方延伸并且在第一和第二互连中的至少一个互连的下表面之下，并且间隔件之间的距离限定气隙的宽度。气隙与第一和第二互连的相邻侧自对准。

22. 发明授权

US06844747B2 Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting 失效
标题翻译：用于生产老化/屏幕的晶片级系统，以及在所有芯片上同时执行的可靠性评估，而不会有任何晶片接触
公开(公告)号：US06844747B2
公开(公告)日：2005-01-18
申请号：US09811915
申请日：2001-03-19
申请人： Wadgi W. Abadeer , William T. Motsiff , Edward J. Nowak
发明人： Wadgi W. Abadeer , William T. Motsiff , Edward J. Nowak
IPC分类号： G01R1/04 , G01R31/28 , G01R31/315 , G01R31/02
CPC分类号： G01R31/2879 , G01R1/0408 , G01R31/2831 , G01R31/315
摘要： A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.
摘要翻译：用于产生老化，电压屏幕和可靠性评估的晶片级系统，其将在所有晶片上同时执行，而不需要在老化/压力期间探测任何晶片的接触。还提供了一种用于实现晶片级产品老化/屏幕的方法，以及根据晶片级系统对半导体芯片的半导体可靠性评估。根据优选方案，晶片的所有芯片同时受压而不需要在应力过程期间探头物理地接触任何芯片。该概念可以应用于产品晶圆的老化，产品晶圆的电压屏以及各种故障机制的可靠性评估。

23. 发明授权

US06798066B1 Heat dissipation from IC interconnects 失效
标题翻译： IC互连散热
公开(公告)号：US06798066B1
公开(公告)日：2004-09-28
申请号：US10249910
申请日：2003-05-16
申请人： William T. Motsiff , Timothy D. Sullivan , Jean E. Wynne , Sally J. Yankee
发明人： William T. Motsiff , Timothy D. Sullivan , Jean E. Wynne , Sally J. Yankee
IPC分类号： H01L2348
CPC分类号： H01L23/60 , H01L23/36 , H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to dissipating heat from an interconnect formed in a low thermal conductivity dielectric in an integrated circuit apparatus. The integrated circuit apparatus includes integrated circuit devices interconnected by conductive interconnection metallurgy and input/output pads subject to electrostatic discharge events. At least one latent heat of transformation absorber is associated with at least one of the input/output pads for preventing the energy generated by an electrostatic discharge event from damaging the conductive interconnection metallurgy.
摘要翻译：本发明涉及从形成在集成电路装置中的低导热电介质中的互连件散热。集成电路装置包括通过导电互连冶金互连的集成电路装置和经受静电放电事件的输入/输出垫。至少一个变换吸收器的潜热与至少一个输入/输出焊盘相关联，用于防止由静电放电事件产生的能量损坏导电互连冶金。

24. 发明授权

US06746947B2 Post-fuse blow corrosion prevention structure for copper fuses 有权
标题翻译：铜熔丝保险丝熔断防腐结构
公开(公告)号：US06746947B2
公开(公告)日：2004-06-08
申请号：US10254277
申请日：2002-09-25
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译：公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。使用镶嵌工艺完成制作。金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。金属结构可用作耐腐蚀保险丝。金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。电阻器结构可以形成在电介质槽的壁上。该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。电阻可以与MOSFET或其他结构串联。

25. 发明授权

US06496053B1 Corrosion insensitive fusible link using capacitance sensing for semiconductor devices 失效
标题翻译：使用半导体器件的电容感测的腐蚀不敏感的熔丝
公开(公告)号：US06496053B1
公开(公告)日：2002-12-17
申请号：US09416977
申请日：1999-10-13
申请人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
发明人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.
摘要翻译：用于编程设备或熔丝的结构和方法包括具有可改变的电容的电容电路。电容电路可以包括第一电容器，连接到第一电容器的熔丝链和连接到熔丝链路的第二电容器，其中去除熔丝链的一部分改变电容。

26. 发明授权

US06455914B2 Pedestal fuse 失效
标题翻译：基座保险丝
公开(公告)号：US06455914B2
公开(公告)日：2002-09-24
申请号：US09842545
申请日：2001-04-26
申请人： Dennis P. Bouldin , Timothy H. Daubenspeck , William T. Motsiff
发明人： Dennis P. Bouldin , Timothy H. Daubenspeck , William T. Motsiff
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines. This applies to wiring layers formed from “high” melting temperature metals and those defined using a damascene process. For example, copper back end of line (Cu BEOL) damascene wiring, as used with CMOS can use the invention. The technique achieves high yield fusing for technologies that use thick wiring layers. The structure separates the thickness of the fuse segment from the remainder of the wiring line. The structure can be used with very thick, e.g., >1.2 &mgr; wiring and very thin, e.g.,
摘要翻译：公开了一种制造金属化熔丝线的结构和方法。该结构可以形成在半导体衬底上，包括形成在衬底上的绝缘体结构，绝缘体结构具有上层和下层，上部比下部更薄，绝缘体结构具有多个不同深度的开口以及镶嵌在绝缘体结构中的金属结构，具有第一和第二部分的金属结构和在其之间的第三部分比第一和第二部分具有更大的阻力，第三部分的厚度基本上类似于上层绝缘体结构。上层包括氮化物，下层包括氧化物，金属结构包括铜。熔丝结构允许在厚金属线段内形成“易于激光删除”的薄金属保险丝。这适用于由“高”熔融金属形成的布线层和使用镶嵌工艺定义的布线层。例如，与CMOS一起使用的铜后端（Cu BEOL）镶嵌布线可以使用本发明。该技术实现了使用厚布线层的技术的高产率熔合。该结构将熔丝段的厚度与布线的其余部分分开。该结构可以使用非常厚的例如>1.2μm的布线和非常薄的例如<0.5μ的保险丝。

27. 发明授权

US07207096B2 Method of manufacturing high performance copper inductors with bond pads 有权
标题翻译：制造具有接合焊盘的高性能铜电感器的方法
公开(公告)号：US07207096B2
公开(公告)日：2007-04-24
申请号：US10707896
申请日：2004-01-22
申请人： Jeffrey P. Gambino , William T. Motsiff , Erick G. Walton
发明人： Jeffrey P. Gambino , William T. Motsiff , Erick G. Walton
IPC分类号： H01F7/127 , H01L21/44
CPC分类号： H01L28/10 , H01F41/041 , H01L21/76852 , H01L21/76885 , H01L23/3192 , H01L23/5227 , H01L23/53238 , H01L24/02 , H01L2224/0401 , H01L2224/13022 , H01L2224/13147 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/0105 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , Y10T29/4902 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.
摘要翻译：一种用于制造高性能铜电感器的方法包括提供在最后的金属层面上形成的高Cu层压螺旋电感器，并且在最后的金属+1级别处，金属层通过棒与第二金属层相互螺旋形形成最后一个金属级螺旋金属电感和最后一个金属+1电平。该方法包括将厚电感器的形成与最后的金属+1布线形成接合焊盘，端子和互连布线。包括介电沉积和间隔物形成步骤，和/或钝化金属如CoWP的选择性沉积，以钝化在最后一个金属层之后形成的Cu电感器。

28. 发明授权

US06991971B2 Method for fabricating a triple damascene fuse 失效
标题翻译：三镶嵌保险丝的制造方法
公开(公告)号：US06991971B2
公开(公告)日：2006-01-31
申请号：US10675177
申请日：2003-09-30
申请人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
发明人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
IPC分类号： H01L21/82
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a second dielectric layer on top of said mandrel and a top surface of said first dielectric layer forming contact openings down to said substrate in said first and second dielectric layers on opposite sides of said mandrel, said contacts spaced away from said mandrel and leaving portions of said second dielectric layer between said mandrel and said contacts; removing said second dielectric layer from over said mandrel between said contact openings to form a trough; and filling said trough and contact openings with a conductor.
摘要翻译：一种制造用于半导体器件的熔丝的方法。该方法包括：提供衬底; 在所述衬底的顶表面上形成第一电介质层; 在所述第一介电层的顶表面上形成介电心轴; 在所述心轴的顶部上形成第二电介质层，并且所述第一电介质层的顶表面在所述心轴的相对侧上的所述第一和第二介电层中向下形成接触开口，所述触头与所述心轴间隔开并留下部分所述第二电介质层位于所述心轴和所述触头之间; 从所述心轴上的所述接触开口之间移除所述第二电介质层以形成槽; 并用导体填充所述槽和接触开口。

29. 发明授权

US06946379B2 Insulative cap for laser fusing 失效
标题翻译：激光熔接绝缘帽
公开(公告)号：US06946379B2
公开(公告)日：2005-09-20
申请号：US10860470
申请日：2004-06-03
申请人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Henry A. Nye, III
发明人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Henry A. Nye, III
IPC分类号： H01L23/525 , H01L23/544 , H01L21/44
CPC分类号： H01L23/544 , H01L23/5258 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.
摘要翻译：一种具有形成在其中的至少一个熔丝和对准标记的半导体器件。在熔断器和对准标记的表面上的抗蚀刻层，其提供与激光熔丝删除工艺结合使用的均匀的钝化厚度。

30. 发明授权

US06924210B1 Chip dicing 失效
标题翻译：芯片切片
公开(公告)号：US06924210B1
公开(公告)日：2005-08-02
申请号：US10708487
申请日：2004-03-06
申请人： Timothy H. Daubenspeck , William T. Motsiff , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , William T. Motsiff , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： B23K26/40 , H01L21/46 , H01L21/78
CPC分类号： H01L21/78 , B23K26/40 , B23K2101/40 , B23K2103/50
摘要： A method and structure for cutting semiconductor chips from a wafer (dicing). For each chip of the wafer, a laser beam is used to cut around the chip along a plurality of straight-line cut segments such that the formed corners of the chip after cutting are all greater than 90°. As a result, the stress at these corners are much less than that of prior art chips, especially during packaging step. In one embodiment, the laser beam is used to cut along only straight-line cut segments not on any chip boundary line, and a saw blade is used to cut along all the chip boundary lines.
摘要翻译：一种从晶片切割半导体芯片的方法和结构（切割）。对于晶片的每个芯片，使用激光束沿着多个直线切割段切割芯片，使得切割后的芯片的形成的角都大于90°。结果，这些拐角处的应力比现有技术的芯片要小得多，特别是在包装步骤中。在一个实施例中，激光束仅用于切割不在任何芯片边界线上的直线切割段，并且锯片用于沿着所有芯片边界线切割。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式