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21. 发明授权

US5222243A Sorting apparatus having plurality of registers with associated multiplexers and comparators for concurrently sorting and storing incoming data according to magnitude 失效
标题翻译：具有相关多路复用器和比较器的多个寄存器的分类设备，用于同时存储和存储根据扩展的入局数据
公开(公告)号：US5222243A
公开(公告)日：1993-06-22
申请号：US478126
申请日：1990-02-09
申请人： Randall D. Briggs , Erin A. Handgen
发明人： Randall D. Briggs , Erin A. Handgen
IPC分类号： G06F7/22 , G06F7/24
CPC分类号： G06F7/24
摘要： Apparatus for receiving and automatically storing data words according to magnitude is provided. A self-sorting stack embodying the invention comprises a sorting device comprising means for simultaneously comparing the incoming data with the contents of each stack register, and logic and switching means for automatically inserting the new data into the correct register on the stack while at the same time pushing the contents of that and subsequent registers down one location. The entire operation is performed in one clock cycle, the same as for a conventional nonsorting stack.

22. 发明授权

US5133049A Accelerated decomposition of small polygons into trapezoids 失效
标题翻译：将小多边形加速分解成梯形
公开(公告)号：US5133049A
公开(公告)日：1992-07-21
申请号：US493185
申请日：1990-03-14
申请人： Bradley W. Cain , Randall D. Briggs
发明人： Bradley W. Cain , Randall D. Briggs
IPC分类号： G06T11/20 , G06T11/40 , G06T17/20
CPC分类号： G06T17/20
摘要： A method and device for improving the processing performance of a transform engine by off-loading the processing of those input polygons which have no more than a predetermined number of edges and decomposing such polygons into trapezoids which can be rendered by a scan conversion system. This is accomplished in accordance with the invention by reading edge data of each input polygon into a RAM and determining the relative positions of the Y coordinates of end points of each edge so that the beginning and end of each respective edge of the polygon in the Y direction may be determined. The polygon is then broken into trapezoids by reading in the respective beginning points of respective edges of the polygon and proceeding until the end point of one of the edges is reached. At the end of one edge, another edge of the polygon is read in, and the process continues until all trapezoids in the polygon have been drawn. Since trapezoids may be much more efficiently handled by the scan conversion system, a significant performance enhancement in the polygon processing is made possible in accordance with the invention.
摘要翻译：一种用于通过对具有不超过预定数量的边缘的那些输入多边形的处理进行卸载来改进变换引擎的处理性能并将这样的多边形分解成可由扫描转换系统呈现的梯形的方法和装置。根据本发明，通过将每个输入多边形的边缘数据读入RAM并确定每个边缘的端点的Y坐标的相对位置，使得Y中的多边形的每个相应边缘的开始和结束方向可以确定。然后通过读取多边形的相应边缘的相应起始点，然后将多边形分解成梯形，直到达到其中一个边缘的终点。在一个边缘的末端，多边形的另一个边缘被读入，并且该过程继续进行，直到多边形中的所有梯形被绘制为止。由于可以通过扫描转换系统更有效地处理梯形，所以根据本发明可以实现多边形处理中的显着性能增强。

23. 发明授权

US08164390B1 Regulating an operating condition of an integrated circuit to compensate for a manufacturing variation 有权
标题翻译：调节集成电路的工作状态以补偿制造变化
公开(公告)号：US08164390B1
公开(公告)日：2012-04-24
申请号：US12048957
申请日：2008-03-14
申请人： Randall D. Briggs , Eran Maor , Walter Lee McNall , William B. Weiser , Haggai Telem
发明人： Randall D. Briggs , Eran Maor , Walter Lee McNall , William B. Weiser , Haggai Telem
IPC分类号： H03L7/081
CPC分类号： H03L7/081
摘要： An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.
摘要翻译：集成电路具有执行操作的操作电路。操作调节器调节操作电路的工作状态。操作调节器具有采样时钟以产生采样时钟信号。采样时钟信号与电子电路的制造变化相关。操作调节器还包括用于评估采样时钟信号并根据评估产生配置信号的配置器。提供控制器以接收配置信号并根据配置信号控制操作电路的操作状态。

24. 发明授权

US08076164B1 On-die bond wires system and method for enhancing routability of a redistribution layer 有权
标题翻译：管芯接合线系统和用于增强再分布层的可路由性的方法
公开(公告)号：US08076164B1
公开(公告)日：2011-12-13
申请号：US12774634
申请日：2010-05-05
申请人： Randall D. Briggs
发明人： Randall D. Briggs
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L24/49 , H01L23/49575 , H01L24/48 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49175 , H01L2224/49176 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/19107 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.
摘要翻译：集成电路包括位于封装中的第一管芯和第二管芯。第一管芯具有在管芯上形成的再分配层，并且包括多个重新定位的接合焊盘。重定位的接合焊盘定位在第一模具的靠近第二模具的内边缘的内边缘附近。每个重新定位的接合焊盘通过相应的接合线耦合到第二管芯上的相应接合焊盘。第一裸片还包括多个原始接合焊盘。再分配层还包括至少一个中间接合焊盘，其通过相应的导电迹线电连接到相应的原始接合焊盘。每个中间接合焊盘通过相应的接合线电连接到相应的重定位接合焊盘。

25. 发明授权

US07945827B1 Method and device for scan chain management of dies reused in a multi-chip package 有权
标题翻译：用于多芯片封装中重复使用的裸片扫描链管理的方法和装置
公开(公告)号：US07945827B1
公开(公告)日：2011-05-17
申请号：US11986529
申请日：2007-11-20
申请人： Randall D. Briggs
发明人： Randall D. Briggs
IPC分类号： G01R31/28
CPC分类号： G01R31/318513 , G01R31/318563
摘要： An apparatus and method for economical testing of dies in a multichip module. Internal I/O pins on a die are logically connected to external I/O pins of the multichip module through the use of a silicon interposer on which the dies are attached. Multiplexers on the interposer can select between the external pins of the multichip module and the internal pins of the dies. The silicon interposer can be economically manufactured using manufacturing technology having relatively a large feature size, such as is found in a relatively mature IC fabrication plant. Further, use of the present invention allows multichip modules to be tested for faults without the necessity of redesigning test circuitry or adding additional pins to the package.
摘要翻译：一种用于在多芯片模块中经济测试模具的装置和方法。芯片上的内部I / O引脚通过使用连接有裸片的硅插入件在逻辑上连接到多芯片模块的外部I / O引脚。插入器上的多路复用器可以在多芯片模块的外部引脚和芯片的内部引脚之间进行选择。可以使用具有相对较大特征尺寸的制造技术经济地制造硅插入器，例如在相对成熟的IC制造工厂中发现的。此外，使用本发明允许对多芯片模块进行故障测试，而无需重新设计测试电路或向封装添加额外的引脚。

26. 发明授权

US5444827A Method and apparatus for preventing print overruns by rasterizing complex page strips using an increased clock frequency 失效
标题翻译：用于通过使用增加的时钟频率光栅化复杂页面条来防止打印超限的方法和装置
公开(公告)号：US5444827A
公开(公告)日：1995-08-22
申请号：US247806
申请日：1994-05-23
申请人： Randall D. Briggs , Greg L. Allen
发明人： Randall D. Briggs , Greg L. Allen
IPC分类号： B41J5/30 , G06F3/12 , G06K15/00 , G06K15/12
CPC分类号： G06K15/12 , G06K15/1823 , G06K15/1848 , G06K2215/0082
摘要： A page printer includes a variable frequency clock for producing at least two clock frequencies, one higher than the other. The page printer includes a first memory for storing a page processing procedure and a second memory for storing data comprising full page strips. A processor operates at the first clock frequency in conjunction with the page processing procedure and derives a rasterization execution time (RET) for display commands that define images to be printed in each page strip of a page. The processor compares the RET for each page strip with a threshold value and rasterizes in the standard manner any page strip whose RET is equal to or less than the threshold value (while operating under the influence of the first clock frequency). When a complex page strip is found (whose RET exceeds the threshold), the variable frequency clock is controlled to generate a second higher frequency clock signal and to cause the processor to operate at a rate determined by the higher clock frequency so that display commands in the complex page strip are rasterized at higher speed.
摘要翻译：页面打印机包括用于产生至少两个时钟频率的可变频率时钟，一个高于另一个。页面打印机包括用于存储页面处理过程的第一存储器和用于存储包括全页条带的数据的第二存储器。处理器在第一时钟频率下与页面处理过程一起操作，并且导出用于定义要在页面的每个页面条中打印的图像的显示命令的光栅化执行时间（RET）。处理器将每个页面条的RET与阈值进行比较，并以标准方式栅格其RET等于或小于阈值（同时在第一个时钟频率的影响下工作）的任何页面条。当发现复杂的页面条（其RET超过阈值）时，控制可变频率时钟以产生第二较高频率时钟信号，并使处理器以由较高时钟频率确定的速率工作，使得显示命令复杂的页面条以更高的速度进行光栅化。

27. 发明授权

US09252119B1 Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of making and using the same 有权
标题翻译：包括再分配层的球栅阵列，包括其的封装集成电路及其制造和使用方法
公开(公告)号：US09252119B1
公开(公告)日：2016-02-02
申请号：US13008160
申请日：2011-01-18
申请人： Randall D. Briggs
发明人： Randall D. Briggs
IPC分类号： H01L23/00
CPC分类号： H01L24/48 , H01L23/49816 , H01L23/49838 , H01L24/02 , H01L2224/05644 , H01L2224/45014 , H01L2224/73215 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a first chip, the first chip including a plurality of bond pads; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, at least one of the plurality of layers being configured to electrically connect the plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the first chip, wherein the redistribution layer is configured to electrically connect at least one of the plurality of bond pad connectors and at least one of the plurality of bond pads on the first chip.
摘要翻译：公开了用于相对低成本的封装集成电路（例如，球栅阵列或BGA封装）的方法，算法，架构，封装，电路和/或方法。例如，封装的集成电路可以包括第一芯片，第一芯片包括多个键合焊盘; 多个接合焊盘连接器，与多个接合焊盘电连通; 具有多个层的衬底，所述多个层中的至少一个被配置为电连接所述多个接合焊盘连接器和多个外部封装连接; 以及在所述第一芯片上的再分布层，其中所述再分配层被配置为电连接所述多个接合焊盘连接器中的至少一个和所述第一芯片上的所述多个接合焊盘中的至少一个。

28. 发明申请

US20150022849A1 Method and Apparatus for Optimizing Memory Usage in an Imaging Device 审中-公开
标题翻译：用于优化成像装置中的存储器使用的方法和装置
公开(公告)号：US20150022849A1
公开(公告)日：2015-01-22
申请号：US13945744
申请日：2013-07-18
申请人： Mark D. Montierth , Randall D. Briggs , Douglas Gene Keithley , David A. Bartle
发明人： Mark D. Montierth , Randall D. Briggs , Douglas Gene Keithley , David A. Bartle
IPC分类号： G06K15/02
CPC分类号： G06K15/1827 , G06F1/3275 , G06F12/0246 , G06F13/102 , G06F2212/1028 , G06F2212/7202 , H04N1/32363 , H04N1/32464 , H04N2201/0082 , H04N2201/3288 , H04N2201/3295 , H04N2201/3297 , Y02D10/13 , Y02D10/14
摘要： A system including a communication interface, a memory, and a processor. The communication interface is configured to receive data. The memory is divided into a first retention region and a second retention region, wherein the first retention region is configured to store data for a first predetermined period of time, and the second retention region is configured to store data for a second predetermined period of time. The processor is configured to i) initially store, within the first retention region of the memory, the data that is received, and ii) in response to the data that is received having been stored in the first retention region of the memory for a time limit that exceeds the first predetermined period of time, transfer the data that is received from the first retention region of the memory to the second retention region of the memory.
摘要翻译：一种包括通信接口，存储器和处理器的系统。通信接口被配置为接收数据。存储器被分成第一保留区域和第二保留区域，其中第一保留区域被配置为在第一预定时间段内存储数据，并且第二保留区域被配置为在第二预定时间段内存储数据。处理器被配置为i）最初在存储器的第一保留区域内存储接收的数据，以及ii）响应于已经存储在存储器的第一保留区域中的数据一段时间限制超过第一预定时间段，将从存储器的第一保留区域接收的数据传送到存储器的第二保留区域。

29. 发明授权

US08332201B1 Innovative verification methodology for deeply embedded computational element 有权
标题翻译：深入嵌入式计算元素的创新验证方法
公开(公告)号：US08332201B1
公开(公告)日：2012-12-11
申请号：US11803781
申请日：2007-05-16
申请人： Randall D. Briggs
发明人： Randall D. Briggs
IPC分类号： G06F17/50
CPC分类号： G06F11/26 , G06F17/5045 , G06F2217/14
摘要： A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.
摘要翻译：提出了一种用于逻辑电路的电路验证方法。该方法包括开发代表逻辑电路的第一硬件描述语言（HDL）代码，并且对于逻辑电路的嵌入部分，开发代表嵌入部分的第二HDL代码。第二HDL代码包括强制嵌入部分的输入到一个或多个已知值的处理。该方法还包括结合第一和第二HDL代码操作处理设备，并响应于强制输入到逻辑电路来验证嵌入部分的操作。

30. 发明授权

US08294940B1 Updating data in a one-time programmable data storage device 有权
标题翻译：更新一次性可编程数据存储设备中的数据
公开(公告)号：US08294940B1
公开(公告)日：2012-10-23
申请号：US12129076
申请日：2008-05-29
申请人： Walter Lee McNall , Randall D. Briggs
发明人： Walter Lee McNall , Randall D. Briggs
IPC分类号： G06K15/00 , G06F3/12
CPC分类号： G06F12/0238 , G06F2212/202
摘要： A system and method are disclosed for updating data stored in a one-time programmable (non-rewritable) non-volatile storage device (“OTP”). The OTP is segmented so that updated data may be written to unused areas. Valid data may be differentiated from stale data using a data recognition technique such as tallying or indexing. According to a tallying technique, an updated event count may be obtained by counting the number of blown bits in the OTP. Each time the event occurs, the next bit is blown. According to an indexing technique, each bit in an index corresponds to a data block in the OTP. When updated data is written to the next (empty) data block in order in the OTP, the corresponding (next) index bit is blown. A valid data set may be located by counting the number of blown bits in the index.
摘要翻译：公开了一种用于更新存储在一次性可编程（非可重写）非易失性存储设备（OTP）中的数据的系统和方法。 OTP被分段，以便更新的数据可能被写入未使用的区域。有效数据可以使用数据识别技术（如统计或索引）与陈旧的数据进行区分。根据计算技术，可以通过对OTP中的比特数进行计数来获得更新的事件计数。每次事件发生时，下一位都将被释放。根据索引技术，索引中的每个比特对应于OTP中的数据块。当更新的数据在OTP中按顺序写入下一个（空）数据块时，相应的（下一个）索引位将被释放。可以通过对索引中的比特数进行计数来定位有效的数据集。

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