专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070158714A1 ONE-MASK HIGH-K METAL-INSULATOR-METAL CAPACITOR INTEGRATION IN COPPER BACK-END-OF-LINE PROCESSING 审中-公开
标题翻译：铜掩模高级金属绝缘子 - 金属电容器集成在铜后处理中
公开(公告)号：US20070158714A1
公开(公告)日：2007-07-12
申请号：US11164382
申请日：2005-11-21
申请人： Ebenezer Eshun , Jessie Abbotts , Daniel Colello , Douglas Coolbaugh , Zhong-Xiang He , Matthew Moon , Charles Musante , Robert Rassel
发明人： Ebenezer Eshun , Jessie Abbotts , Daniel Colello , Douglas Coolbaugh , Zhong-Xiang He , Matthew Moon , Charles Musante , Robert Rassel
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/76895
摘要： A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical connections to both electrodes of the MIM capacitor are made via conventional BEOL metallization, requiring no additional dedicated process steps. The bottom plates (formed of gate conductor material) of the MIM capacitors overlie STI regions formed at the same time as STI regions between transistors. Method and apparatus are described.
摘要翻译：描述了MIM电容器技术，其中底板（电极）由栅极导体材料构成，并且以相同的方式使用与晶体管栅极相同的掩模和处理步骤形成在相同的层中。顶板（电极）使用简单的单掩模，单镶嵌工艺形成。与MIM电容器的两个电极的电连接通过常规BEOL金属化制成，不需要额外的专用工艺步骤。 MIM电容器的底板（由栅极导体材料形成）覆盖与晶体管之间的STI区域同时形成的STI区域。描述了方法和装置。

22. 发明申请

US20070065966A1 PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
标题翻译：单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺
公开(公告)号：US20070065966A1
公开(公告)日：2007-03-22
申请号：US11162661
申请日：2005-09-19
申请人： Anil Chinthakindi , Douglas Coolbaugh , Keith Downes , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper
发明人： Anil Chinthakindi , Douglas Coolbaugh , Keith Downes , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper
IPC分类号： H01L21/00 , H01L29/84
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

23. 发明申请

US20070057343A1 INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS 有权
标题翻译：金属栅极或硅化物上的MIM电容器与高K电介质材料的集成
公开(公告)号：US20070057343A1
公开(公告)日：2007-03-15
申请号：US11162471
申请日：2005-09-12
申请人： Anil Chinthakindi , Douglas Coolbaugh , Keith Downes , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper , Kunal Vaed
发明人： Anil Chinthakindi , Douglas Coolbaugh , Keith Downes , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper , Kunal Vaed
IPC分类号： H01L29/00
CPC分类号： H01L28/40
摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.
摘要翻译：金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱与半导体衬底共面。辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。在MIM电容器下板上形成电容器HiK电介质层。在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

24. 发明申请

US20060249848A1 TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME 有权
公开(公告)号：US20060249848A1
公开(公告)日：2006-11-09
申请号：US10908346
申请日：2005-05-09
申请人： Douglas Coolbaugh , Daniel Edelstein , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper
发明人： Douglas Coolbaugh , Daniel Edelstein , Ebenezer Eshun , Zhong-Xiang He , Robert Rassel , Anthony Stamper
IPC分类号： B32B7/12
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

25. 发明申请

US20060166454A1 LOW TOLERANCE POLYSILICON RESISTOR FOR LOW TEMPERATURE SILICIDE PROCESSING 失效
标题翻译：用于低温硅酮加工的低耐压多晶硅电阻器
公开(公告)号：US20060166454A1
公开(公告)日：2006-07-27
申请号：US10905940
申请日：2005-01-27
申请人： Douglas Coolbaugh , John Florkey , Robert Rassel
发明人： Douglas Coolbaugh , John Florkey , Robert Rassel
IPC分类号： H01L21/20
CPC分类号： H01L21/26513 , H01L27/0802 , H01L28/20
摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.
摘要翻译：提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。激活可以通过沉积保护性介电层或单独的激活退火来进行。在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

26. 发明申请

US20060152333A1 HEAT SINK FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：集成电路设备的散热
公开(公告)号：US20060152333A1
公开(公告)日：2006-07-13
申请号：US10905546
申请日：2005-01-10
申请人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
发明人： Douglas Coolbaugh , Ebenezer Eshun , Terence Hook , Robert Rassel , Edmund Sprogis , Anthony Stamper , William Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

27. 发明申请

US20060046418A1 METHOD OF ADJUSTING RESISTORS POST SILICIDE PROCESS 失效
标题翻译：硅胶工艺后调整电阻的方法
公开(公告)号：US20060046418A1
公开(公告)日：2006-03-02
申请号：US10711130
申请日：2004-08-26
申请人： Douglas Coolbaugh , Heidi Greer , Robert Rassel
发明人： Douglas Coolbaugh , Heidi Greer , Robert Rassel
IPC分类号： H01L21/20
CPC分类号： H01L21/2652 , H01C17/26 , H01C17/265 , H01L28/20
摘要： A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.
摘要翻译：提供了在硅化后测量和调整电阻器的电阻值的电阻器的制造方法。本发明的方法首先开始在半导体衬底的表面上提供具有电阻值的至少一个电阻器，例如多晶硅。至少一个电阻器已进行硅化处理。接下来，测量至少一个电阻器的电阻值，以确定硅化后电阻器的实际电阻。在测量步骤之后，调整电阻器的电阻以获得所需的电阻值。调整可以包括后硅化快速热退火和/或后硅化离子注入和低温快速热退火步骤。

28. 发明申请

US20070241421A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 失效
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070241421A1
公开(公告)日：2007-10-18
申请号：US11279934
申请日：2006-04-17
申请人： Xuefeng Liu , Robert Rassel , Steven Voldman
发明人： Xuefeng Liu , Robert Rassel , Steven Voldman
IPC分类号： H01L21/331 , H01L29/00
CPC分类号： H01L29/7322 , H01L27/0921 , H01L29/0821 , H01L29/66272
摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.
摘要翻译：一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。至少一个通孔电连接深子集电极和近子集电极。该方法包括形成合并三阱双外延/双子集电极。

29. 发明申请

US20070096260A1 REDUCED PARASITIC AND HIGH VALUE RESISTOR AND METHOD OF MANUFACTURE 审中-公开
标题翻译：降低PARASITIC和高价值电阻及其制造方法
公开(公告)号：US20070096260A1
公开(公告)日：2007-05-03
申请号：US11163741
申请日：2005-10-28
申请人： Ebenezer Eshun , Robert Rassel
发明人： Ebenezer Eshun , Robert Rassel
IPC分类号： H01L27/082
CPC分类号： H01L27/0802 , H01L23/5228 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a device includes forming a dielectric layer on a substrate and forming a resistor on the dielectric layer. A second dielectric layer formed over the resistor is etched to expose edge portions of the resistor. The edge portions of the resistor are doped through the openings. A contact is formed in the openings. A device is also provided.
摘要翻译：一种制造器件的方法包括在衬底上形成电介质层并在电介质层上形成电阻器。形成在电阻器上方的第二介电层被蚀刻以暴露电阻器的边缘部分。电阻器的边缘部分通过开口掺杂。在开口中形成接触。还提供了一种设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式