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21. 发明授权

US07890818B2 Read level control apparatuses and methods 有权
公开(公告)号：US07890818B2
公开(公告)日：2011-02-15
申请号：US12010043
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
发明人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G11C29/42 , G06F11/1068 , G11C11/5628 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

22. 发明授权

US07639539B2 Method and apparatus for programming data of memory cells considering floating poly coupling 有权
标题翻译：考虑浮动聚合耦合的存储器单元的数据编程方法和装置
公开(公告)号：US07639539B2
公开(公告)日：2009-12-29
申请号：US11905674
申请日：2007-10-03
申请人： Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Nam Phil Jo , Sung Chung Park , Seung-Hwan Song
发明人： Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Nam Phil Jo , Sung Chung Park , Seung-Hwan Song
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： A method and an apparatus for programming data of memory cells considering coupling are provided. The method includes: calculating a change of a threshold voltage based on source data of the memory cells; converting source data which will be programmed based on the calculated change of the threshold voltage; and programming the converted source data.
摘要翻译：提供了考虑耦合的存储器单元的数据编程方法和装置。该方法包括：基于存储器单元的源数据计算阈值电压的变化; 基于所计算的阈值电压的变化来转换将被编程的源数据; 并对转换的源数据进行编程。

23. 发明申请

US20090027238A1 Apparatuses and methods for encoding and decoding 有权
标题翻译：用于编码和解码的装置和方法
公开(公告)号：US20090027238A1
公开(公告)日：2009-01-29
申请号：US12010025
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
发明人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
IPC分类号： H03M7/00
CPC分类号： H03M13/235 , H03M13/6561
摘要： A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.
摘要翻译：码编码装置包括延迟电路和码发生器。延迟电路基于并行接收的p位输入信息产生延迟信息。延迟信息根据时钟生成。代码生成器基于输入信息和延迟信息中的至少一个生成n.p位代码，其中n是有理数。

24. 发明申请

US20080276149A1 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US20080276149A1
公开(公告)日：2008-11-06
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G06F11/07
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

25. 发明申请

US20080244339A1 Read level control apparatuses and methods 有权
标题翻译：读取电平控制装置和方法
公开(公告)号：US20080244339A1
公开(公告)日：2008-10-02
申请号：US12010043
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
发明人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G06F11/1068 , G11C11/5628 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.
摘要翻译：提供各种读取级别控制装置和方法。在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及读数据。该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

26. 发明申请

US20090231914A1 Memory devices and methods 有权
标题翻译：内存设备和方法
公开(公告)号：US20090231914A1
公开(公告)日：2009-09-17
申请号：US12232150
申请日：2008-09-11
申请人： Donghun Yu , Kyoung Lae Cho , Dongku Kang , Dong Hyuk Chae , Jun Jin Kong
发明人： Donghun Yu , Kyoung Lae Cho , Dongku Kang , Dong Hyuk Chae , Jun Jin Kong
IPC分类号： G11C16/06 , G11C16/00
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2029/0411 , G11C2211/5621
摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.
摘要翻译：公开了一种存储器件和存储器数据读取方法。存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔，单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压检测到错误位。

27. 发明授权

US08020081B2 Multi-level cell memory devices using trellis coded modulation and methods of storing data in and reading data from the memory devices 有权
标题翻译：使用网格编码调制的多级单元存储器件以及将数据存储在存储器件中并从其读取数据的方法
公开(公告)号：US08020081B2
公开(公告)日：2011-09-13
申请号：US11802334
申请日：2007-05-22
申请人： Jun Jin Kong , Sung Chung Park , Yun Tae Lee , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun , Dong Ku Kang
发明人： Jun Jin Kong , Sung Chung Park , Yun Tae Lee , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun , Dong Ku Kang
IPC分类号： H03M13/03
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/10
摘要： A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.
摘要翻译：多级单元（MLC）存储器件可以包括：MLC存储器单元; 外部编码器，其使用第一编码方案对数据进行编码以生成外部编码比特流; 以及网格编码调制（TCM）调制器，其向MLC存储器单元施加编程脉冲以将数据写入MLC存储器单元。可以通过对外部编码比特流进行TCM调制来生成编程脉冲。一种在MLC存储器件中存储数据，从MLC存储器件读取数据或将数据存储在MLC存储器件中并从MLC存储器件读取数据的方法可以包括：使用第一编码方案对数据进行编码以产生外编码位流; 以及向MLC存储器件的MLC存储器单元施加编程脉冲以将数据写入MLC存储单元。可以通过对外部编码比特流进行TCM调制来生成编程脉冲。

28. 发明申请

US20110213930A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20110213930A1
公开(公告)日：2011-09-01
申请号：US13067099
申请日：2011-05-09
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G06F12/08
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

29. 发明授权

US07957475B2 Dual carrier modulation (DCM) demapper and DCM demapping method 有权
标题翻译：双载波调制（DCM）解映射器和DCM解映射方法
公开(公告)号：US07957475B2
公开(公告)日：2011-06-07
申请号：US11704907
申请日：2007-02-12
申请人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
发明人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
IPC分类号： H04K1/10
CPC分类号： H04L27/2649 , H04L25/022 , H04L25/067 , H04L27/3416
摘要： A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
摘要翻译：提供DCM解映射器和DCM解映射方法。 DCM解映射器包括：使用信号和两个子载波的信道信息生成多个基本信号的基本信号生成单元; 软判决生成单元，使用所述多个基本信号生成多个软判决; 以及软判决选择单元，在所生成的软决策中选择与所述两个子载波的每个比特相对应的软判决。

30. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

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