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21. 发明授权

US5834834A Module mounting and adhesion systems and methods for electronic modules 失效
标题翻译：模块安装和电子模块的附着系统和方法
公开(公告)号：US5834834A
公开(公告)日：1998-11-10
申请号：US347662
申请日：1994-12-01
申请人： Robert D. Lee , Steven Hass , Michael L. Bolan , Hal Kurkowski
发明人： Robert D. Lee , Steven Hass , Michael L. Bolan , Hal Kurkowski
IPC分类号： G05B23/02 , G06F3/023 , G06F3/038 , G06F13/18 , G06K7/00 , G06K19/04 , G06K19/06 , G06K19/07 , G06K19/077 , G08C19/00 , G11C5/00 , G11C5/06 , G11C7/24 , G11C8/20 , H01L23/02 , H01L23/04
CPC分类号： G11C8/20 , G06F3/0383 , G06F3/04897 , G06K19/04 , G06K19/047 , G06K19/07 , G06K19/0706 , G06K19/0723 , G06K19/07735 , G06K19/07743 , G06K7/0008 , G06K7/0021 , G06K7/0086 , G11C11/41 , G11C5/005 , G11C5/066 , G11C5/141 , G11C7/24 , G11C8/10
摘要： The present invention relates to mounting and adhesion systems and methods for compact electronic modules. More particularly, the present invention relates to an apparatus and technique for mounting an electronic module that is capable of communicating with an interface unit on a one-way-bus.
摘要翻译：本发明涉及紧凑型电子模块的安装和附着系统和方法。更具体地，本发明涉及一种用于安装能够与单向总线上的接口单元通信的电子模块的装置和技术。

22. 发明授权

US5627361A Wand for reading and writing information to electronic tokens 失效
标题翻译：用于将信息读取和写入电子令牌的魔杖
公开(公告)号：US5627361A
公开(公告)日：1997-05-06
申请号：US355389
申请日：1994-12-13
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： G05B23/02 , G06F3/023 , G06F3/038 , G06F13/18 , G06K7/00 , G06K19/04 , G06K19/06 , G06K19/07 , G06K19/077 , G08C19/00 , G11C5/00 , G11C5/06 , G11C7/24 , G11C8/20 , G06K7/10
CPC分类号： G11C8/20 , G06F3/0383 , G06F3/04897 , G06K19/04 , G06K19/047 , G06K19/07 , G06K19/0706 , G06K19/0723 , G06K19/07735 , G06K19/07743 , G06K7/0008 , G06K7/0021 , G06K7/0086 , G11C11/41 , G11C5/005 , G11C5/066 , G11C5/141 , G11C7/24 , G11C8/10
摘要： A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module test the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the value of the bit read.
摘要翻译：通过单线总线提供与便携式数据模块的有效数据通信的系统架构，其不一定包括任何精确的时间延迟电路。模块中的延时电路可能非常粗糙。采用集电开关结构，电气关系被定义为绝对最小化便携式模块电池的漏电。已经指定了一个协议，使得该模块永远不会向当前的单线总线的数据线供电，但只能吸收电流。该协议包括用于读取的信号; 写零; 写一个并重置。每个一位事务由来自主机的电压信号的下降沿启动。模块中的延时电路定义了延迟，之后（在写模式下）模块测试数据线的数据状态。在读取模式下，在来自主机的电压信号的下降沿之后，模块根据读取的位的值进行或不导通下拉晶体管。因此，主机系统在下降沿之后，尝试再次将数据线拉高，然后测试数据线的电位以确定读取的位的值。

23. 发明授权

US5526274A Digital potentiometer with stackable configuration system 失效
标题翻译：数字电位器，具有堆叠配置系统
公开(公告)号：US5526274A
公开(公告)日：1996-06-11
申请号：US89923
申请日：1993-07-09
申请人： Michael L. Bolan , Robert D. Lee , Gary V. Zanders
发明人： Michael L. Bolan , Robert D. Lee , Gary V. Zanders
IPC分类号： G05B24/02 , H04R25/00 , G01N27/04
CPC分类号： H03M1/007 , G05B24/02 , H03M1/682 , H03M1/765 , H03M1/804
摘要： An system containing an integrated circuit having two separate potentiometers combined on a single substrate; each potentiometer having three separate output terminals, two being connected to the ends of a resistor string, and the third being a "wiper" terminal electrically connected to a point within the length of the resistor string. All three terminals of each potentiometer electrically float with respect to the other pins of the integrated circuit. Control logic is used to select the point in the resistor string where the wiper terminal is to connect. An additional control signal is used to connect an additional wiper to one of the two separate wiper terminals permitting the connection of the two resistor strings in series.
摘要翻译：一种包含集成电路的系统，其具有组合在单个基板上的两个单独的电位器; 每个电位器具有三个单独的输出端子，两个连接到电阻器串的端部，第三个是电连接到电阻器串长度内的点的“擦拭器”端子。每个电位器的所有三个端子相对于集成电路的其他引脚电浮动。控制逻辑用于选择雨刷端子要连接的电阻串中的点。附加的控制信号用于将另外的擦拭器连接到允许串联连接两个电阻器串的两个分离的刮水器端子中的一个。

24. 发明授权

US5513235A Integrated circuit thermometer 失效
公开(公告)号：US5513235A
公开(公告)日：1996-04-30
申请号：US327736
申请日：1994-10-24
申请人： James M. Douglass , Gary V. Zanders , Robert D. Lee
发明人： James M. Douglass , Gary V. Zanders , Robert D. Lee
IPC分类号： G01K1/02 , G01K7/24 , G06F1/20 , G01K7/32
CPC分类号： G06F1/206 , G01K1/028 , G01K7/245
摘要： An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

25. 发明授权

US5398326A Method for data communication 失效
标题翻译：数据通信方法
公开(公告)号：US5398326A
公开(公告)日：1995-03-14
申请号：US019932
申请日：1993-02-19
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： G05B23/02 , G06F3/023 , G06F3/038 , G06F13/18 , G06K7/00 , G06K19/04 , G06K19/06 , G06K19/07 , G06K19/077 , G08C19/00 , G11C5/00 , G11C5/06 , G11C7/24 , G11C8/20
CPC分类号： G11C8/20 , G06F3/0383 , G06F3/04897 , G06K19/04 , G06K19/047 , G06K19/07 , G06K19/0706 , G06K19/0723 , G06K19/07735 , G06K19/07743 , G06K7/0008 , G06K7/0021 , G06K7/0086 , G11C11/41 , G11C5/005 , G11C5/066 , G11C5/141 , G11C7/24 , G11C8/10
摘要： A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the value of the bit read.
摘要翻译：通过单线总线提供与便携式数据模块的有效数据通信的系统架构，其不一定包括任何精确的时间延迟电路。模块中的延时电路可能非常粗糙。采用集电开关结构，电气关系被定义为绝对最小化便携式模块电池的漏电。已经指定了一个协议，使得该模块永远不会向当前的单线总线的数据线供电，但只能吸收电流。该协议包括用于读取的信号; 写零; 写一个并重置。每个一位事务由来自主机的电压信号的下降沿启动。模块中的延时电路定义了一个延迟，之后（在写入模式下）模块测试数据线的数据状态。在读取模式下，在来自主机的电压信号的下降沿之后，模块根据读取的位的值进行或不导通下拉晶体管。因此，主机系统在下降沿之后，尝试再次将数据线拉高，然后测试数据线的电位以确定读取的位的值。

26. 发明授权

US5315549A Memory controller for nonvolatile RAM operation, systems and methods 失效
标题翻译：用于非易失性RAM操作的内存控制器，系统和方法
公开(公告)号：US5315549A
公开(公告)日：1994-05-24
申请号：US714545
申请日：1991-06-11
申请人： Francis A. Scherpenberg , Eric W. Mumper , John W. Rea , Robert D. Lee
发明人： Francis A. Scherpenberg , Eric W. Mumper , John W. Rea , Robert D. Lee
IPC分类号： G11C5/14 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C5/141 , G11C7/04 , Y10T307/832
摘要： A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.
摘要翻译：当主电源电压与可编程加电源故障写保护一起下降时，用于提供备用电池电源的存储器控制器。该控制器包括超级诱导睡眠模式操作，基于电池电压级别的备用操作期间备用电池之间的MOS切换以及用于电池处理的放电电路。

27. 发明授权

US5297268A ID protected memory with a readable/writable ID template 失效
标题翻译： ID保护的内存与可读/可写的ID模板
公开(公告)号：US5297268A
公开(公告)日：1994-03-22
申请号：US622297
申请日：1990-12-04
申请人： Robert D. Lee , Hal Kurkowski
发明人： Robert D. Lee , Hal Kurkowski
IPC分类号： G06F12/14
CPC分类号： G06F12/1466
摘要： A CPU (28) accesses remotely disposed RAM (12) through a common serial data link. The RAM is interfaced to the common data link under the control of an arbiter circuit (10). The arbiter includes a protocol shift register (31) for receiving control information, ID information, and address information for the RAM. The incoming ID information is compared with an ID template (37), and:If a match IS present:Read/Write access to the RAM is allowed, andRead/Write access to the ID template is allowed;If a match is NOT present:NO access to the RAM is allowed,Read-Only access to the ID template is allowed.
摘要翻译： CPU（28）通过公共串行数据链路访问远程放置的RAM（12）。在调节器电路（10）的控制下，RAM与公共数据链路相连。仲裁器包括用于接收RAM的控制信息，ID信息和地址信息的协议移位寄存器（31）。将进入的ID信息与ID模板（37）进行比较，并且：如果存在匹配IS：允许对RAM的读/写访问，并且允许对ID模板的读/写访问; 如果不存在匹配项：不允许访问RAM，只允许访问ID模板。

28. 发明授权

US4955038A Low-power RF receiver 失效
标题翻译：低功率射频接收机
公开(公告)号：US4955038A
公开(公告)日：1990-09-04
申请号：US282819
申请日：1988-12-09
申请人： Robert D. Lee , Robert W. Mounger , John P. Heptig
发明人： Robert D. Lee , Robert W. Mounger , John P. Heptig
IPC分类号： H04B1/16
CPC分类号： H04W52/0277 , H04W52/029 , H04W52/0216 , Y02B60/50
摘要： A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator.Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized.Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.
摘要翻译： RF接收机具有极低的待机功耗。为了最小化待机时的功耗，天线电路（包括谐振腔）的模拟输入直接连接到比较器的输入端。优选地，使用两个比较器，每个连接到单独的天线。因此，由于天线零点的信号损失将被最小化。优选地，后级解码脉冲宽度调制（或突发长度调制）信号。如果脉冲长度基本上超过预期的最大值，则下一级提供控制信号以减小输入比较器的增益。

29. 发明授权

US4935645A Fusing and detection circuit 失效
标题翻译：熔断和检测电路
公开(公告)号：US4935645A
公开(公告)日：1990-06-19
申请号：US163082
申请日：1988-03-02
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： G11C7/24 , G11C8/20 , G11C17/16 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C7/24 , G11C8/20
摘要： A fusing and detection circuit includes a diode fusing element which is coupled to a fuse input terminal of an integrated circuit. Upon the application of the proper voltage at the fuse input terminal, the fuse element is blown, causing the diode to become a low impedance resistor. The detection circuitry senses whether the fuse has been blown or not and provides a lock or unlock indication at an output terminal. The fusing and detection circuit is designed to thwart attempts to change the lock status to an unlock status after the fuse has been blown.
摘要翻译：熔断和检测电路包括耦合到集成电路的熔丝输入端的二极管熔断元件。在保险丝输入端施加适当的电压时，熔丝元件被熔断，导致二极管成为低阻抗电阻。检测电路检测保险丝是否已经熔断，并在输出端提供锁定或解锁指示。熔断器和检测电路设计用于在保险丝熔断之后，阻止将锁定状态更改为解锁状态的尝试。

30. 发明授权

US4634890A Clamping circuit finding particular application between a single sided output of a computer memory and a differential amplifier sensing circuit 失效
标题翻译：钳位电路在计算机存储器的单面输出和差分放大器感测电路之间寻求特殊应用
公开(公告)号：US4634890A
公开(公告)日：1987-01-06
申请号：US648092
申请日：1984-09-06
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： G11C7/12 , G11C11/4094 , H03K5/02 , H03K17/16
CPC分类号： H03K5/023 , G11C11/4094 , G11C7/12
摘要： A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal.
摘要翻译：一种用于钳位半导体存储器的输出节点的晶体管装置，包括与传输门并联以产生差分输出信号的反相器。

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