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21. 发明授权

US5598094A Current mirror 失效
标题翻译：电流镜
公开(公告)号：US5598094A
公开(公告)日：1997-01-28
申请号：US301867
申请日：1994-09-06
申请人： Oliver Kiehl , Rudolf Koch
发明人： Oliver Kiehl , Rudolf Koch
IPC分类号： G05F3/26 , G05F3/20
CPC分类号： G05F3/26
摘要： A current mirror includes first through eighteenth transistors. The load paths of the first and second transistors are in series for carrying an input current to a first supply potential. The control terminals of the first through eighth transistors receive the input current. The load paths of the fourth, third, ninth and tenth transistors are in series between the first and a second supply potential. The third and ninth transistors form a tap being connected to the control terminals of the ninth, tenth, eleventh, twelfth and thirteenth transistors. The load paths of the fifth, sixth, eleventh and fourteenth transistors are in series between the first and second supply potentials. The sixth and eleventh transistors form a tap being connected to the control terminals of the fourteenth through sixteenth transistors. The load paths of the seventeenth, seventh, twelfth and fifteenth transistors are in series between the first and second supply potentials. The seventh and twelfth transistors form a tap being connected to the control terminals of the seventeenth and eighteenth transistors. The load paths of the eighteenth and eighth transistors are in series for tapping a first output current proportional to the input current from the first supply potential. The load paths of the sixteenth and thirteenth transistors are in series for tapping a second output current equal to the first from the second supply potential. The ninth through sixteenth transistors are of one, and the seventeenth, eighteenth and first through eighth transistors being of the other, conduction type.
摘要翻译：电流镜包括第一至第十八晶体管。第一和第二晶体管的负载路径是串联的，用于将输入电流传送到第一电源电位。第一至第八晶体管的控制端接收输入电流。第四，第三，第九和第十晶体管的负载路径串联在第一和第二供电电位之间。第三和第九晶体管形成连接到第九，十，十一，十二和十三个晶体管的控制端的抽头。第五，第六，第十一和第十四晶体管的负载路径串联在第一和第二电源电位之间。第六和第十六晶体管形成连接到第十四至第十六晶体管的控制端的抽头。第十七，第十二，第十五和第十五晶体管的负载路径串联在第一和第二供电电位之间。第七和第十二晶体管形成连接到第十七和第十八晶体管的控制端的抽头。第十八和第八晶体管的负载路径是串联的，用于分流与来自第一电源电位的输入电流成比例的第一输出电流。第十六和第十三晶体管的负载路径是串联的，用于从第二电源电位抽出等于第一输出电流的第二输出电流。第九至第十六晶体管是一个，并且第十七，十八和第一至第八晶体管是另一个导电类型。

22. 发明申请

US20130141124A1 TEST METHOD OF DRIVING APPARATUS AND CIRCUIT TESTING INTERFACE THEREOF 有权
标题翻译：驱动装置和电路测试接口的测试方法
公开(公告)号：US20130141124A1
公开(公告)日：2013-06-06
申请号：US13308569
申请日：2011-12-01
申请人： Bret Dale , Oliver Kiehl
发明人： Bret Dale , Oliver Kiehl
IPC分类号： G01R31/00
CPC分类号： G01R31/2889 , G01R31/2884
摘要： A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad.
摘要翻译：公开了一种电路测试接口和测试方法。电路测试接口可以包括测试电流传输焊盘，测试电压测量焊盘和包括输出端子的至少一个驱动电路。至少一个驱动电路的输出端可以耦合到穿硅通孔（TSV）。电路测试接口还可以包括耦合到（1）驱动电路的输出端，（2）测试电流传输焊盘和（3）测试电压测量板的至少一个开关模块。

23. 发明授权

US08138610B2 Multi-chip package with interconnected stacked chips 有权
标题翻译：具有互连堆叠芯片的多芯片封装
公开(公告)号：US08138610B2
公开(公告)日：2012-03-20
申请号：US12028542
申请日：2008-02-08
申请人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
发明人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L25/03 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01079 , H01L2224/05599
摘要： A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
摘要翻译：提供了具有至少第一，第二和第三芯片的多芯片封装，每个芯片包括顶部和底部表面。多芯片封装还具有用于与印刷电路板（PCB）连接的封装基板。芯片和封装衬底容纳在封装材料内。第一芯片的底表面附接到封装衬底。第一芯片的顶表面具有第一多个着陆焊盘，其用作第一和第二芯片之间的机械和电接口。第二芯片的底表面具有用作第二芯片和第一芯片之间的机械和电接口的第二多个着陆焊盘。此外，第二芯片的顶表面具有用作第二和第三芯片之间的机械和电接口的第三多个着陆焊盘。

24. 发明授权

US07636250B2 Random access memory that selectively provides data to amplifiers 失效
标题翻译：有选择地向放大器提供数据的随机存取存储器
公开(公告)号：US07636250B2
公开(公告)日：2009-12-22
申请号：US11487875
申请日：2006-07-17
申请人： Jiyoon Chung , Oliver Kiehl
发明人： Jiyoon Chung , Oliver Kiehl
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C2207/005
摘要： A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. The first circuit is configured to receive the first data via the first data path and the second data via the second data path. The first circuit is configured to selectively provide the first data to the first amplifier and the second amplifier and the second data to the first amplifier and the second amplifier.
摘要翻译：一种包括第一放大器，第二放大器，第一数据路径，第二数据路径和第一电路的随机存取存储器。第一数据路径经由第一存储单元接收第一数据，第二数据路径经由第二存储单元接收第二数据。第一电路经配置以经由第一数据路径和第二数据经由第二数据路径接收第一数据。第一电路被配置为向第一放大器和第二放大器选择性地提供第一数据，并将第二数据提供给第一放大器和第二放大器。

25. 发明授权

US07539034B2 Memory configured on a common substrate 有权
标题翻译：存储器配置在公共基板上
公开(公告)号：US07539034B2
公开(公告)日：2009-05-26
申请号：US11701006
申请日：2007-02-01
申请人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
发明人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
IPC分类号： G11C5/00 , G11C5/06 , H01L23/34
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H05K1/181 , H01L2224/0401
摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
摘要翻译：存储器包括第一宏芯片，脊芯片和公共基板。公共基板被配置为在第一宏芯片和脊芯片之间传递信号。第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

26. 发明申请

US20090129186A1 SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS 失效
标题翻译：用于检测错误的自诊断方案
公开(公告)号：US20090129186A1
公开(公告)日：2009-05-21
申请号：US11943428
申请日：2007-11-20
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G11C29/12
CPC分类号： G11C5/04 , G11C29/44 , G11C29/789 , G11C2029/0401 , G11C2029/1208 , G11C2229/726 , G11C2229/743 , H01L25/0657 , H01L25/18 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
摘要翻译：本发明通常涉及集成电路器件，更具体地说，涉及包含用于检测MCP中的错误的自诊断方案的多芯片封装（MCP）的方法和系统。 MCP通常包括控制器，具有错误检测逻辑的至少一个易失性存储器芯片，至少一个非易失性存储器芯片以及用于存储与在MCP中检测到的存储器错误相关的失败签名数据的至少一个故障签名寄存器。控制器可以轮询失败签名寄存器以获取与其中存储的存储器错误有关的失败签名数据。在检测到失败签名数据时，控制器可以将故障签名数据存储在位于非易失性存储器上的故障签名寄存器上。

27. 发明申请

US20060143330A1 Method for data transmit burst length control 审中-公开
标题翻译：数据传输突发长度控制方法
公开(公告)号：US20060143330A1
公开(公告)日：2006-06-29
申请号：US11021704
申请日：2004-12-23
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Method for controlling the burst length of a data transmission. A preferred embodiment comprises initiating a fixed burst length transmission and issuing a burst terminate command specifying a desired length of the burst data transfer, wherein the burst terminate command is issued prior to the completion of the fixed burst length data transfer. The burst terminate command specifies an address of a final data to be transferred by the fixed burst length transmission.
摘要翻译：用于控制数据传输的突发长度的方法。优选实施例包括启动固定突发长度传输并发出指定突发数据传输的期望长度的突发终止命令，其中在完成固定突发长度数据传输之前发出突发终止命令。突发终止命令指定要通过固定突发长度传输传送的最终数据的地址。

28. 发明授权

US07042206B2 Integrated circuit and method for operating the integrated circuit 失效
公开(公告)号：US07042206B2
公开(公告)日：2006-05-09
申请号：US10245629
申请日：2002-09-17
申请人： Oliver Kiehl , Hermann Ruckerbauer
发明人： Oliver Kiehl , Hermann Ruckerbauer
IPC分类号： G01R23/175 , H04L1/22
CPC分类号： G11C29/022 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , H04L1/205
摘要： An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and assess a phase shift between one of the digital signals and the time reference signal. A receiver circuit is connected to a respective junction between one of the connecting pads and an associated output driver. A device for matching propagation times of signals applied to the receiver circuit is provided. The assessment circuit is connected to the receiver circuit and has an output to output a measured result. In each case, the phase shift of the signals to be output in relation to the time reference signal is measured and assessed separately. An offset of the switching edges of the signals to be output can be determined relatively accurately and corrected.

29. 发明授权

US06914851B1 Circuit element with timing control 有权
标题翻译：具有定时控制的电路元件
公开(公告)号：US06914851B1
公开(公告)日：2005-07-05
申请号：US10620092
申请日：2003-07-15
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： G11C7/12 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4094 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/12 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4094
摘要： A circuit element has an input for receiving an external clock with a clock period duration. A unit is provided to present the circuit element with information representing the clock period duration of the external clock. In addition the circuit element includes a unit for the temporal control of a signal in the circuit element on the basis of information representing the clock period duration.
摘要翻译：电路元件具有用于接收具有时钟周期持续时间的外部时钟的输入。提供一个单元以向电路元件呈现表示外部时钟的时钟周期持续时间的信息。另外，电路元件包括用于基于表示时钟周期持续时间的信息对电路元件中的信号进行时间控制的单元。

30. 发明授权

US06894933B2 Buffer amplifier architecture for semiconductor memory circuits 有权
标题翻译：用于半导体存储器电路的缓冲放大器架构
公开(公告)号：US06894933B2
公开(公告)日：2005-05-17
申请号：US10759103
申请日：2004-01-20
申请人： Maksim Kuzmenka , Oliver Kiehl
发明人： Maksim Kuzmenka , Oliver Kiehl
IPC分类号： G11C7/10 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C11/4093
摘要： A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal from the buffer amplifier architecture at the input and at the output of the buffer amplifier architecture, and takes the phase difference between the two signals to produce a control signal for setting the variable delay time of the delay circuits. To ensure that the delay time set by the delay detector circuit is independent of variations in parameters of the DRAM memory chips, the feedback path routed to the input of the delay detector circuit has a reference line network of the same structure and having the same electrical properties as capacitance elements which terminate the line network routed to the DRAM memory chips and the reference line network, and which have the same capacitances as the signal inputs on the DRAM memory chips.
摘要翻译：公开了一种用于缓冲在半导体存储器模块上并行提供给相同芯片，特别是DRAM芯片的信号的缓冲放大器架构。该结构具有每个信号线中的可调延迟电路和延迟检测器电路，其在缓冲放大器架构的输入和输出处接收来自缓冲放大器架构的时钟信号，并且采用两个信号之间的相位差产生用于设置延迟电路的可变延迟时间的控制信号。为了确保由延迟检测器电路设置的延迟时间与DRAM存储器芯片的参数变化无关，路由到延迟检测器电路的输入端的反馈路径具有相同结构的参考线网络并且具有相同的电属性作为终止线路网络路由到DRAM存储器芯片和参考线网络的电容元件，并且具有与DRAM存储器芯片上的信号输入相同的电容。

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