专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07310399B1 Clock signal circuitry for multi-protocol high-speed serial interface circuitry 有权
公开(公告)号：US07310399B1
公开(公告)日：2007-12-18
申请号：US11650163
申请日：2007-01-05
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H04L25/40
CPC分类号： G06F1/10
摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

22. 发明授权

US07002368B2 Programmable logic device with high speed serial interface circuitry 有权
公开(公告)号：US07002368B2
公开(公告)日：2006-02-21
申请号：US11128916
申请日：2005-05-12
申请人： Chong H. Lee , Reza Asayesh
发明人： Chong H. Lee , Reza Asayesh
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17732
摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

23. 发明授权

US06943588B1 Dynamically-adjustable differential output drivers 有权
标题翻译：动态可调差分输出驱动器
公开(公告)号：US06943588B1
公开(公告)日：2005-09-13
申请号：US10670146
申请日：2003-09-24
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

24. 发明授权

US06911841B2 Programmable logic device with high speed serial interface circuitry 有权
公开(公告)号：US06911841B2
公开(公告)日：2005-06-28
申请号：US10643276
申请日：2003-08-18
申请人： Chong H. Lee , Reza Asayesh
发明人： Chong H. Lee , Reza Asayesh
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732
摘要： A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that can be supported are XAUI, InfiniBand, 1G Ethernet, FibreChannel, and Serial RapidIO. The HSSI circuitry may be partly programmable to support these various standards. In some cases control may come from the associated PLD core circuitry. Also in some cases some of the interface functions may be performed in the PLD core circuitry.

25. 发明申请

US20100277201A1 EMBEDDED DIGITAL IP STRIP CHIP 审中-公开
标题翻译：嵌入式数字IP条带芯片
公开(公告)号：US20100277201A1
公开(公告)日：2010-11-04
申请号：US12434606
申请日：2009-05-01
申请人： Curt Wortman , Chong H. Lee , Richard G. Cliff
发明人： Curt Wortman , Chong H. Lee , Richard G. Cliff
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84 , H03K19/17724 , H03K19/17732
摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.
摘要翻译：提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。第二区包括标准逻辑单元和基本单元。在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。在一个实施例中，第二区域可以嵌入第一区域。在另一个实施例中，第二区域围绕第一区域的周边限定。可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用40G / 100G替换用于基于计算的应用的诸如PCI Express的原始功能以太网和因特拉肯，用于有线应用。还提供了一种设计集成电路的方法。

26. 发明授权

US07675326B1 Dynamically-adjustable differential output drivers 失效
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07675326B1
公开(公告)日：2010-03-09
申请号：US12163709
申请日：2008-06-27
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

27. 发明授权

US07039787B1 Byte alignment circuitry 失效
标题翻译：字节对齐电路
公开(公告)号：US07039787B1
公开(公告)日：2006-05-02
申请号：US10984684
申请日：2004-11-09
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/4018 , H04J3/0608
摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.
摘要翻译：用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。如果字节对齐电路随后检测到提示可能需要新的或改变的字节对齐的信息，则输出第二状态信号。然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

28. 发明授权

US06867616B1 Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
标题翻译：具有双用途锁相环电路的可编程逻辑器件串行接口
公开(公告)号：US06867616B1
公开(公告)日：2005-03-15
申请号：US10455773
申请日：2003-06-04
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H03K19/173 , H03D3/24
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
摘要翻译：在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

29. 发明授权

US08363770B1 Oversampling with programmable pointer adjustment 有权
标题翻译：可编程指针调整过采样
公开(公告)号：US08363770B1
公开(公告)日：2013-01-29
申请号：US11555570
申请日：2006-11-01
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H04L12/50
CPC分类号： H04L7/0338 , H04L7/0331
摘要： Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.
摘要翻译：系统，方法和电路在存在噪声和/或抖动的情况下从过采样数据流中提取数据。指针决定提取过采样数据流的哪些数据样本。在数据转换之后发生的一些指针基于先前指针的位置而定位，而不是使用在对齐期间发生的数据转换点。诸如指针与数据转换对齐频率的频率以及在对准期间的最大调整量的设置可以是可编程的。

30. 发明授权

US07940814B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07940814B2
公开(公告)日：2011-05-10
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04J3/04
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式