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21. 发明授权

US06498104B1 Method of in-situ cleaning for LPCVD TEOS pump 失效
标题翻译： LPCVD TEOS泵原位清洗方法
公开(公告)号：US06498104B1
公开(公告)日：2002-12-24
申请号：US09776308
申请日：2001-02-02
申请人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato
发明人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato
IPC分类号： H01L21311
CPC分类号： C23C16/4412 , C23C16/4405 , C23C16/4407
摘要： In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition including at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.
摘要翻译：在一个实施方案中，本发明涉及清洗其中包含TEOS材料的低压化学气相沉积设备的方法，其中包括使低压化学气相沉积设备与含有至少一种低级醇的组合物接触。在另一个实施方案中，本发明涉及用于清洗其中含有TEOS材料的低压化学气相沉积设备的系统，其中含有至少一种低级醇的组合物; 用于将包含至少一种低级醇的组合物引入低压化学气相沉积装置的注入口; 以及用于从低压化学气相沉积装置中除去结晶的TEOS材料积聚的泵/真空系统。

22. 发明授权

US06458212B1 Mesh filter design for LPCVD TEOS exhaust system 失效
标题翻译： LPCVD TEOS排气系统的滤网设计
公开(公告)号：US06458212B1
公开(公告)日：2002-10-01
申请号：US09539393
申请日：2000-03-31
申请人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato , Jayendra Bhakta
发明人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato , Jayendra Bhakta
IPC分类号： C23C1600
CPC分类号： C23C16/4412 , Y10S55/30
摘要： One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.
摘要翻译：本发明的一个方面涉及一种四乙基原硅酸盐化学气相沉积方法，包括以下步骤：在化学气相沉积室中使用原硅酸四乙酯在基底上形成膜; 以及经由泵系统和连接到化学气相沉积室的排气管线从化学气相沉积室除去原硅酸四乙酯副产物，排气管线包括具有圆锥形状的网状过滤器。本发明的另一方面涉及一种用于从化学气相沉积室除去原硅酸四乙酯副产物的排气系统，该排气系统包含连接到化学气相沉积室的排气管线，该排气管线包括经由泵系统具有锥形形状的网状过滤器; 以及与排气管连接以从处理室除去原硅酸四乙酯副产物的泵系统。

23. 发明授权

US06184084B2 Method to elimate silicide cracking for nand type flash memory devices by implanting a polish rate improver into the second polysilicon layer and polishing it 有权
标题翻译：通过将抛光速率改进剂注入第二多晶硅层并抛光来消除n型闪存器件的硅化物裂纹的方法
公开(公告)号：US06184084B2
公开(公告)日：2001-02-06
申请号：US09263701
申请日：1999-03-05
申请人： David Chi , Kent Kuohua Chang , Yuesong He
发明人： David Chi , Kent Kuohua Chang , Yuesong He
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/3212
摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH4; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.
摘要翻译：在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层; 通过沉积具有第一厚度的第二多晶硅层，然后使用化学机械抛光形成具有第二厚度的第二多晶硅层，在所述绝缘层上形成第二多晶硅层，其中所述第二厚度比所述第二厚度小至少约25％第一厚度通过使用WF6和SiH4的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

24. 发明授权

US5981339A Narrower erase distribution for flash memory by smaller poly grain size 失效
标题翻译：通过较小的晶粒尺寸来减少闪存的擦除分布
公开(公告)号：US5981339A
公开(公告)日：1999-11-09
申请号：US45013
申请日：1998-03-20
申请人： Kent Kuohua Chang , David Chi , Yuesong He
发明人： Kent Kuohua Chang , David Chi , Yuesong He
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L21/8247
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/4916 , H01L29/511 , H01L29/518 , H01L29/66825
摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of: forming a tunnel oxide on a substrate; forming an in situ phosphorus doped polysilicon layer over the tunnel oxide by low pressure chemical vapor deposition at a temperature between about 610.degree. C. and about 630.degree. C., wherein the in situ phosphorus doped polysilicon layer comprises from about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.19 atoms/cm.sup.3 of phosphorus; forming an insulating layer over the in situ phosphorus doped polysilicon layer; forming a conductive layer over the insulating layer; etching the in situ phosphorus doped polysilicon layer, the conductive layer and the insulating layer, thereby defining one or more stacked gate structures; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structures, thereby forming one or more memory cells.
摘要翻译：在一个实施例中，本发明涉及一种形成闪存单元的方法，该方法包括以下步骤：在衬底上形成隧道氧化物; 在约610℃至约630℃的温度下通过低压化学气相沉积在隧道氧化物上形成原位磷掺杂多晶硅层，其中原位磷掺杂多晶硅层包含约1×1019原子/ cm3至约5×1019原子/ cm3磷; 在原位磷掺杂多晶硅层上形成绝缘层; 在所述绝缘层上形成导电层; 蚀刻原位磷掺杂多晶硅层，导电层和绝缘层，从而限定一个或多个堆叠栅极结构; 以及在所述衬底中形成源区和漏区，其中所述源极区和所述漏区由所述堆叠栅极结构自对准，从而形成一个或多个存储单元。

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