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21. 发明授权

US07453123B2 Self-aligned planar double-gate transistor structure 有权
标题翻译：自对平面双栅晶体管结构
公开(公告)号：US07453123B2
公开(公告)日：2008-11-18
申请号：US11676030
申请日：2007-02-16
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

22. 发明授权

US07413941B2 Method of fabricating sectional field effect devices 有权
标题翻译：制造截面场效应装置的方法
公开(公告)号：US07413941B2
公开(公告)日：2008-08-19
申请号：US11433806
申请日：2006-05-13
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

23. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

24. 发明授权

US07091069B2 Ultra thin body fully-depleted SOI MOSFETs 失效
标题翻译：超薄体全耗尽SOI MOSFET
公开(公告)号：US07091069B2
公开(公告)日：2006-08-15
申请号：US10710273
申请日：2004-06-30
申请人： Bruce B. Doris , Meikei Ieong , Zhibin Ren , Paul M. Solomon , Min Yang
发明人： Bruce B. Doris , Meikei Ieong , Zhibin Ren , Paul M. Solomon , Min Yang
IPC分类号： H01L27/01 , H01L21/00 , H01L21/356
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772
摘要： A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.
摘要翻译：提供了一种制造超薄体全耗尽SOI SOI的方法，其中SOI厚度随着栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

25. 发明授权

US07659153B2 Sectional field effect devices and method of fabrication 有权
标题翻译：截面场效应器件及其制造方法
公开(公告)号：US07659153B2
公开(公告)日：2010-02-09
申请号：US12142849
申请日：2008-06-20
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

26. 发明授权

US07388258B2 Sectional field effect devices 有权
标题翻译：截面场效应装置
公开(公告)号：US07388258B2
公开(公告)日：2008-06-17
申请号：US10732322
申请日：2003-12-10
申请人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
发明人： Ying Zhang , Bruce B. Doris , Thomas Safron Kanarsky , Meikei Ieong , Jakub Tadeusz Kedzierski
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

27. 发明授权

US07094634B2 Structure and method for manufacturing planar SOI substrate with multiple orientations 失效
公开(公告)号：US07094634B2
公开(公告)日：2006-08-22
申请号：US10710277
申请日：2004-06-30
申请人： Huilong Zhu , Bruce B. Doris , Meikei Ieong , Phillip J. Oldiges , Min Yang
发明人： Huilong Zhu , Bruce B. Doris , Meikei Ieong , Phillip J. Oldiges , Min Yang
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/76254 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/84 , H01L29/045 , H01L29/785 , Y10T428/249921 , Y10T428/249922
摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

28. 发明授权

US07691482B2 Structure for planar SOI substrate with multiple orientations 失效
标题翻译：具有多个取向的平面SOI衬底的结构
公开(公告)号：US07691482B2
公开(公告)日：2010-04-06
申请号：US11473835
申请日：2006-06-23
申请人： Huilong Zhu , Bruce B. Doris , Meikei Ieong , Philip J. Oldiges , Min Yang
发明人： Huilong Zhu , Bruce B. Doris , Meikei Ieong , Philip J. Oldiges , Min Yang
IPC分类号： B32B9/04 , H01L27/12
CPC分类号： H01L21/76254 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/84 , H01L29/045 , H01L29/785 , Y10T428/249921 , Y10T428/249922
摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.
摘要翻译：本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

29. 发明申请

US20080318374A1 Metal Gated Ultra Short MOSFET Devices 失效
公开(公告)号：US20080318374A1
公开(公告)日：2008-12-25
申请号：US12198857
申请日：2008-08-26
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

30. 发明授权

US07348629B2 Metal gated ultra short MOSFET devices 有权
标题翻译：金属门极超短MOSFET器件
公开(公告)号：US07348629B2
公开(公告)日：2008-03-25
申请号：US11407473
申请日：2006-04-20
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

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