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21. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

22. 发明申请

US20050070056A1 SOI template layer 有权
标题翻译： SOI模板层
公开(公告)号：US20050070056A1
公开(公告)日：2005-03-31
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

23. 发明申请

US20110156051A1 SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS 有权
标题翻译：具有低漏电肖特基接触的半导体器件
公开(公告)号：US20110156051A1
公开(公告)日：2011-06-30
申请号：US13042948
申请日：2011-03-08
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L29/20 , H01L21/28 , H01L29/772
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译：实施例包括具有低泄漏肖特基接触的半导体器件。通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

24. 发明申请

US20090146191A1 LOW LEAKAGE SCHOTTKY CONTACT DEVICES AND METHOD 有权
标题翻译：低泄漏肖特基接触器件和方法
公开(公告)号：US20090146191A1
公开(公告)日：2009-06-11
申请号：US11950820
申请日：2007-12-05
申请人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L29/00 , H01L21/338
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1). By minimizing the process steps between opening the Schottky contact window (35) in the passivation layer (25) and forming the Schottky contact (42-1) material in this window (35), the gate leakage of a resulting field effect device (51-5) having a Schottky gate (42-1) is substantially reduced.
摘要翻译：半导体器件描述了方法和装置。方法（100）包括提供包括衬底（21）的部分完成的半导体器件（31-1），在衬底（21）上的半导体（22）和半导体（22）上的钝化层（25）并且使用第一掩模（32）局部蚀刻钝化层（25）以暴露半导体（22）的一部分（36），并且不移除形成肖特基接触（42-1）的第一掩模（32）在所述半导体（22）的暴露部分（36）上的第一材料，然后去除所述第一掩模（32）并使用另外的掩模（44），形成第二材料的步进栅极导体（48-1）耦合到与肖特基触点（42-1）相邻的钝化层（25）的肖特基接触（42-1）和上覆部分（25-1）。通过最小化打开钝化层（25）中的肖特基接触窗（35）并在该窗口（35）中形成肖特基接触（42-1）材料之间的工艺步骤，得到的场效应器件（51）的栅极泄漏 -5）具有肖特基门（42-1）。

25. 发明申请

US20070176227A1 MOS device with nano-crystal gate structure 有权
标题翻译：具有纳米晶体栅结构的MOS器件
公开(公告)号：US20070176227A1
公开(公告)日：2007-08-02
申请号：US11343624
申请日：2006-01-30
申请人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：为非易失性半导体器件提供了方法和装置。该装置包括其中具有源极区域和漏极区域的衬底，漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括：基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层和覆盖一个以上杂质阻挡层的栅极导体层。最靠近栅极导体的阻挡层也可用于调节器件的阈值电压和/或从栅极导体层延迟掺杂剂扩散。

26. 发明申请

US20060237746A1 GeSOI transistor with low junction current and low junction capacitance and method for making the same 有权
标题翻译：具有低结电流和低结电容的GeSOI晶体管及其制造方法
公开(公告)号：US20060237746A1
公开(公告)日：2006-10-26
申请号：US11110234
申请日：2005-04-20
申请人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
发明人： Marius Orlowski , Sinan Goktepeli , Chun-Li Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/7624 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.
摘要翻译：本文提供了一种包括包含锗的衬底（103）的半导体器件（101）。衬底具有限定在其中的源极（107）和漏极（109）。包括具有比锗更高的带隙（E））的第一材料的阻挡层（111）设置在所述源极和漏极区域中的至少一个的边界处。源区和漏区中的至少一个包括锗。

27. 发明申请

US20060040433A1 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US20060040433A1
公开(公告)日：2006-02-23
申请号：US10919952
申请日：2004-08-17
申请人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

28. 发明申请

US20050260807A1 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US20050260807A1
公开(公告)日：2005-11-24
申请号：US10851347
申请日：2004-05-21
申请人： Marius Orlowski , Chun-Li Liu , Choh-Fei Yeap
发明人： Marius Orlowski , Chun-Li Liu , Choh-Fei Yeap
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/7834 , H01L29/78606 , H01L29/78639 , H01L29/78687
摘要： Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device such as for providing different materials for optimizing carrier mobility between N and P channel transistors and for a raised source/drain of silicon in the case of a silicon germanium body.
摘要翻译：硅碳被用作锗的扩散阻挡层，从而可以随后形成硅层而不被锗污染。这在硅硅层分离的同时，硅和硅锗希望存在于同一半导体器件上，例如为了提供不同的材料以优化N沟道晶体管和P沟道晶体管之间的载流子迁移率，在硅锗体的情况下硅的源极/漏极。

29. 发明申请

US20050070057A1 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US20050070057A1
公开(公告)日：2005-03-31
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
发明人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

30. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

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