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21. 发明授权

US06407009B1 Methods of manufacture of uniform spin-on films 有权
标题翻译：均匀旋涂膜的制造方法
公开(公告)号：US06407009B1
公开(公告)日：2002-06-18
申请号：US09190722
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Richard J. Huang
发明人： Lu You , Dawn Hopper , Richard J. Huang
IPC分类号： H01L2130
CPC分类号： H01L21/02134 , B05D1/005 , H01L21/02282 , H01L21/3124
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

22. 发明授权

US06387825B2 Solution flow-in for uniform deposition of spin-on films 有权
标题翻译：溶液流入用于均匀沉积旋涂膜
公开(公告)号：US06387825B2
公开(公告)日：2002-05-14
申请号：US09191435
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Richard J. Huang
发明人： Lu You , Dawn Hopper , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , B05D1/005 , H01L21/02282 , H01L21/312 , H01L21/3124
摘要： This invention describes improved apparatus and methods for spin-on deposition of thin films applicable to the manufacture of semiconductor devices. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了适用于制造半导体器件的薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的薄膜可用于制造包括层间电介质材料的半导体器件。

23. 发明授权

US5861677A Low RC interconnection 失效
标题翻译：低RC互连
公开(公告)号：US5861677A
公开(公告)日：1999-01-19
申请号：US890905
申请日：1997-07-10
申请人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , B29B13/00 , B05D3/02 , H01L21/283
CPC分类号： H01L23/3142 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.
摘要翻译：低阻抗延迟互连图案由诸如铜的低电阻率金属和诸如有机聚合物的低介电常数材料形成。在使用粘合促进剂的低电阻率金属和低介电常数材料之间形成中间粘合层，例如硅烷类粘合促进剂。粘合促进剂可以施加在金属和电介质层之间或并入电介质层中。

24. 发明授权

US08629535B2 Mask for forming integrated circuit 有权
标题翻译：用于形成集成电路的掩模
公开(公告)号：US08629535B2
公开(公告)日：2014-01-14
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L23/58
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

25. 发明授权

US07183198B2 Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes 有权
标题翻译：用于形成使用多个独立形成的封盖材料层以减少针孔的硬掩模的方法
公开(公告)号：US07183198B2
公开(公告)日：2007-02-27
申请号：US10962907
申请日：2004-10-12
申请人： Pei-Yuan Gao , Lu You , Richard J. Huang
发明人： Pei-Yuan Gao , Lu You , Richard J. Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

26. 发明授权

US06875664B1 Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material 失效
标题翻译：在无定形碳和ARC材料之间具有渐变过渡的无定形碳ARC叠层的形成
公开(公告)号：US06875664B1
公开(公告)日：2005-04-05
申请号：US10230794
申请日：2002-08-29
申请人： Richard J. Huang , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/312 , H01L21/314 , H01L21/3213 , H01L21/336
CPC分类号： H01L21/3145 , H01L21/02115 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/312 , H01L21/3144 , H01L21/3146 , H01L21/32139
摘要： A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.
摘要翻译：使用无定形碳硬掩模形成集成电路的方法包括在导电材料层之上提供无定形碳材料层，并在无定形碳材料上方提供抗反射涂层（ARC）材料层。在无定形碳材料层和ARC材料层之间形成过渡区域。过渡区域具有提供无定形碳材料层和ARC材料层之间的转变的浓度分布。去除非晶碳材料层，ARC材料层和过渡区域的一部分以形成硬掩模，并且根据硬掩模在导电材料层中形成特征。

27. 发明授权

US6030901A Photoresist stripping without degrading low dielectric constant materials 有权
标题翻译：光阻胶剥离而不降低低介电常数材料
公开(公告)号：US6030901A
公开(公告)日：2000-02-29
申请号：US339381
申请日：1999-06-24
申请人： Dawn Hopper , Richard J. Huang , Jacques Bertrand , Lu You
发明人： Dawn Hopper , Richard J. Huang , Jacques Bertrand , Lu You
IPC分类号： H01L21/311 , H01L21/312 , H01L21/768 , H01L21/3065
CPC分类号： H01L21/31138 , H01L21/31116 , H01L21/312 , H01L21/3124 , H01L21/76807
摘要： Photoresist masks are stripped using a H.sub.2 -N.sub.2 plasma to prevent increasing the dielectric constant of an exposed carbon-containing dielectric material. Embodiments of the present invention include forming a low dielectric constant, carbon-containing layer, e.g., a polymeric layer, on an exposed metal feature overlying a wafer, forming a photoresist mask on the dielectric layer, forming an opening in the dielectric layer exposing the metal feature and a portion of the dielectric layer, preheating the wafer and stripping the photoresist mask using the H.sub.2 -N.sub.2 plasma.
摘要翻译：使用H 2 -N 2等离子体剥离光刻胶掩模，以防止暴露的含碳介电材料的介电常数增加。本发明的实施例包括在覆盖在晶片上的暴露的金属特征上形成低介电常数的含碳层，例如聚合物层，在电介质层上形成光致抗蚀剂掩模，在电介质层中形成露出暴露于金属特征和电介质层的一部分，预热晶片并使用H 2 -N 2等离子体剥离光致抗蚀剂掩模。

28. 发明授权

US5760480A Low RC interconnection 失效
公开(公告)号：US5760480A
公开(公告)日：1998-06-02
申请号：US530658
申请日：1995-09-20
申请人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , B29B13/00 , B05D3/02 , H01L21/283
CPC分类号： H01L23/3142 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

29. 发明授权

US06133619A Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics 有权
标题翻译：集成电路级间介质中氮氧化硅薄膜的分层还原
公开(公告)号：US06133619A
公开(公告)日：2000-10-17
申请号：US144521
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
发明人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
IPC分类号： H01L21/312 , H01L21/314 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/3124 , H01L21/3145
摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.
摘要翻译：从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制电介质间隙填充层上的介电覆盖层。实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500，从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

30. 发明授权

US07169711B1 Method of using carbon spacers for critical dimension (CD) reduction 失效
标题翻译：使用碳间隔物进行临界尺寸（CD）还原的方法
公开(公告)号：US07169711B1
公开(公告)日：2007-01-30
申请号：US10170984
申请日：2002-06-13
申请人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
发明人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337
摘要： A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
摘要翻译：使用碳间隔物进行临界尺寸减小的方法可以包括在基底上提供图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有第一宽度的孔，在光致抗蚀剂层上沉积碳膜并蚀刻沉积的碳膜以形成间隔物在图案化光致抗蚀剂层的孔的侧壁上，使用所形成的间隔物和图案化的光致抗蚀剂层作为图案蚀刻衬底，以形成具有第二宽度的沟槽，并使用氧化蚀刻去除图案化的光致抗蚀剂层和形成的间隔物。

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