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21. 发明授权

US07276932B2 Power-gating cell for virtual power rail control 有权
标题翻译：用于虚拟电源轨控制的电源门控单元
公开(公告)号：US07276932B2
公开(公告)日：2007-10-02
申请号：US10926597
申请日：2004-08-26
申请人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K19/23
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译：虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。控制信号在单元边界被锁存或响应于时钟信号锁存。

22. 发明授权

US06980018B2 Self limiting gate leakage driver 失效
标题翻译：自限制闸极泄漏驱动器
公开(公告)号：US06980018B2
公开(公告)日：2005-12-27
申请号：US10835501
申请日：2004-04-29
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/003 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲区的逻辑功能，无需驱动大负载。第二和第三逻辑路径具有直到最后一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器可以是逆变器，非逆变器，或提供多输入逻辑功能。

23. 发明申请

US20090027065A1 Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance 失效
标题翻译：用于评估存储阵列性能的字线到位线输出定时环形振荡器电路
公开(公告)号：US20090027065A1
公开(公告)日：2009-01-29
申请号：US11781994
申请日：2007-07-24
申请人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
发明人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
IPC分类号： G01R27/28
CPC分类号： G11C29/50 , G01R31/31937 , G11C29/50012 , G11C2029/1202 , G11C2029/1204
摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.
摘要翻译：用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。存储阵列的列以环形连接，形成环形振荡器。每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。

24. 发明申请

US20080141006A1 System and Method for Implementing Simplified Arithmetic Logic Unit Processing of Value-Based Control Dependence Sequences 有权
标题翻译：用于实现基于价值的控制依赖序列的简化算术逻辑单元处理的系统和方法
公开(公告)号：US20080141006A1
公开(公告)日：2008-06-12
申请号：US11608907
申请日：2006-12-11
申请人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F9/302
CPC分类号： G06F9/3885 , G06F7/575 , G06F9/30021 , G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3857
摘要： A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.
摘要翻译：用于实现算术逻辑单元（ALU）的系统和方法支持基于值的控制依赖序列。根据本发明的第一实施例，ALU产生指定第一和第二值中的一个作为较大值的进位输出信号。响应于进位信号，ALU用第三个值更新存储位置，该值是较大的值。根据本发明的第二实施例，ALU产生指定第一和第二值中的一个作为较大值的进位信号。响应于进位信号，ALU用第三个值更新存储位置。如果进位信号指定第二值作为较大值，则第三值是第四值，如果进位信号指定第一值作为较大值或第三值是第五值。

25. 发明授权

US06872991B1 Low gate-leakage virtual rail circuit 失效
标题翻译：低栅极泄漏虚拟轨道电路
公开(公告)号：US06872991B1
公开(公告)日：2005-03-29
申请号：US10840708
申请日：2004-05-06
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/00 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H03K19/0016
摘要： Circuits within a logic domain use partitioned power supply buses. Selected of the power supply buses are coupled to the power supply voltage potentials with electronic switches with gradated conductivity and leakage current. When the circuits are actively switching during a logic operation, the power supply voltage potentials are coupled to the buses with maximum conductivity. At predetermined times later, selected of the electronic switches are switched OFF to reduce leakage current. Lower conductivity and thus lower leakage switches remain ON to ensure corresponding logic states are maintained during a controlled low leakage time period. Various logic configurations are used to switch OFF high leakage devices.
摘要翻译：逻辑域内的电路使用分区电源总线。选择的电源总线通过具有梯度电导率和漏电流的电子开关耦合到电源电压电位。当电路在逻辑运行期间主动切换时，电源电压电位以最大导电率耦合到总线。在预定时间后，选择的电子开关被切断以减少漏电流。较低的电导率和因此较低的漏电开关保持ON，以确保在受控的低泄漏时间段期间保持相应的逻辑状态。各种逻辑配置用于关闭高泄漏设备。

26. 发明申请

US20080115019A1 Circuit Timing Monitor Having A Selectable-Path Ring Oscillator 失效
标题翻译：具有可选择路径环形振荡器的电路定时监视器
公开(公告)号：US20080115019A1
公开(公告)日：2008-05-15
申请号：US11559436
申请日：2006-11-14
申请人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31725 , G01R31/31726
摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.
摘要翻译：具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换。选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。将功能逻辑块的其他输入设置为预定的一组逻辑值。可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

27. 发明授权

US07288975B2 Method and apparatus for fail-safe and restartable system clock generation 失效
公开(公告)号：US07288975B2
公开(公告)日：2007-10-30
申请号：US11260563
申请日：2005-10-27
申请人： Hung C. Ngo , Gary D. Carpenter , Fadi H. Gebara , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Fadi H. Gebara , Jente B. Kuang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/04
摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

28. 发明授权

US06963250B2 Voltage controlled oscillator with selectable frequency ranges 失效
标题翻译：压控振荡器，频率范围可选
公开(公告)号：US06963250B2
公开(公告)日：2005-11-08
申请号：US10718062
申请日：2003-11-20
申请人： Hung C. Ngo , Gary D. Carpenter
发明人： Hung C. Ngo , Gary D. Carpenter
IPC分类号： H03K3/03 , H03L7/099 , H03B27/00
CPC分类号： H03K3/0315 , H03L7/0995 , H03L7/0997 , H03L2207/06
摘要： A VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. A latch and multiplexer is used to select between two or more outputs within the ring oscillator to change the basic frequency range of the VCO glitch free. To achieve a wide range VCO, additional stages are added to the basic ring oscillator. When the number of stages is an odd number greater than seven, then the voltage controlled feedforward inverting stages feedback to the outputs of the first and second inverting stages of the ring oscillator. Two additional multiplexers are added to select which feedforward inverting stage is coupled to the first and second inverting stage. This allows a wide range interleaved VCO that switches between frequency ranges glitch free.
摘要翻译：使用环形振荡器配置VCO，该环形振荡器具有耦合在构成基本环形振荡器的反相级周围的电压控制的前馈反相级，以使得环形振荡器的频率能够被电压控制。锁存器和多路复用器用于在环形振荡器内的两个或更多个输出之间进行选择，以改变VCO毛刺的基本频率范围。为了实现宽范围的VCO，在基本环形振荡器中增加了额外的级。当级数大于7的奇数时，电压控制的前馈反相级反馈到环形振荡器的第一和第二反相级的输出端。添加两个附加多路复用器以选择哪个前馈反相级耦合到第一和第二反相级。这允许在频率范围无毛刺之间切换的宽范围交错VCO。

29. 发明授权

US07810000B2 Circuit timing monitor having a selectable-path ring oscillator 失效
标题翻译：具有可选路径环形振荡器的电路定时监视器
公开(公告)号：US07810000B2
公开(公告)日：2010-10-05
申请号：US11559436
申请日：2006-11-14
申请人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
IPC分类号： G01R31/3181 , G01R31/30
CPC分类号： G01R31/31727 , G01R31/31725 , G01R31/31726
摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.
摘要翻译：具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换。选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。将功能逻辑块的其他输入设置为预定的一组逻辑值。可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

30. 发明授权

US07667513B2 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US07667513B2
公开(公告)日：2010-02-23
申请号：US10988454
申请日：2004-11-12
申请人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
发明人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

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