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21. 发明授权

US07176718B1 Organizations of logic modules in programmable logic devices 有权
标题翻译：可编程逻辑器件中逻辑模块的组织
公开(公告)号：US07176718B1
公开(公告)日：2007-02-13
申请号：US11040457
申请日：2005-01-21
申请人： Michael D Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
发明人： Michael D Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
摘要翻译：在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。这种分组中的逻辑元素被划分为至少两个子组。提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用比对方。

22. 发明授权

US07368944B1 Organizations of logic modules in programmable logic devices 有权
标题翻译：可编程逻辑器件中逻辑模块的组织
公开(公告)号：US07368944B1
公开(公告)日：2008-05-06
申请号：US11649748
申请日：2007-01-03
申请人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
发明人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
摘要翻译：在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。这种分组中的逻辑元素被划分为至少两个子组。提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用比对方。

23. 发明授权

US07693700B1 Caching technique for electrical simulation of VLSI interconnect 失效
标题翻译： VLSI互连电气仿真缓存技术
公开(公告)号：US07693700B1
公开(公告)日：2010-04-06
申请号：US10462031
申请日：2003-06-13
申请人： Tim Vanderhoek , David Lewis
发明人： Tim Vanderhoek , David Lewis
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/82
摘要： Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.
摘要翻译：包括互连寄生效应的电路，方法和设备，而不会大大增加电路仿真的复杂性和运行时间。基于路径宽度，长度或其他参数，互连路径减少到许多简化拓扑之一。输入驱动波形类似地近似。预先形成网格阵列，其中网格阵列中的每个点对应于与路径拓扑，输入波形和所得到的输出波形相关的一组值。简化的互连路径和输入波形被映射到对应于预定网格阵列中的位置的一组参数中。输出波形通过从位置周围的网格点内插输出波形来确定。

24. 发明授权

US08138786B2 Apparatus and methods for adjusting performance of integrated circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US08138786B2
公开(公告)日：2012-03-20
申请号：US12534101
申请日：2009-07-31
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K19/173 , H03K3/01
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

25. 发明申请

US20070069764A1 APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE OF INTEGRATED CIRCUITS 有权
标题翻译：调整集成电路性能的装置和方法
公开(公告)号：US20070069764A1
公开(公告)日：2007-03-29
申请号：US11535065
申请日：2006-09-26
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang Liu , Bruce Pedersen
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

26. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

27. 发明申请

US20090289696A1 Apparatus and Methods for Adjusting Performance of Integrated Circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US20090289696A1
公开(公告)日：2009-11-26
申请号：US12534101
申请日：2009-07-31
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

28. 发明授权

US07573317B2 Apparatus and methods for adjusting performance of integrated circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US07573317B2
公开(公告)日：2009-08-11
申请号：US11535065
申请日：2006-09-26
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

29. 发明授权

US07304499B1 Distributed random access memory in a programmable logic device 有权
标题翻译：可编程逻辑器件中的分布式随机存取存储器
公开(公告)号：US07304499B1
公开(公告)日：2007-12-04
申请号：US11454815
申请日：2006-06-16
申请人： David Lewis , Paul Leventis , Vaughn Betz
发明人： David Lewis , Paul Leventis , Vaughn Betz
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.
摘要翻译：可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。单个写入路径用于提供配置数据和用户写入数据。选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计时交替传输晶体管。

30. 发明授权

US07129745B2 Apparatus and methods for adjusting performance of integrated circuits 有权
公开(公告)号：US07129745B2
公开(公告)日：2006-10-31
申请号：US10865402
申请日：2004-06-10
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

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