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21. 发明授权

US06303475B1 Methods of fabricating silicon carbide power devices by controlled annealing 有权
标题翻译：通过控制退火制造碳化硅功率器件的方法
公开(公告)号：US06303475B1
公开(公告)日：2001-10-16
申请号：US09451640
申请日：1999-11-30
申请人： Alexander Suvorov , John W. Palmour , Ranbir Singh
发明人： Alexander Suvorov , John W. Palmour , Ranbir Singh
IPC分类号： H01L21336
CPC分类号： H01L29/7816 , H01L21/0445 , H01L21/046 , H01L29/1608 , H01L29/66068 , H01L29/7801 , H01L29/7802 , Y10S438/965
摘要： Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650° C., but preferably more than about 1500°. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500° C. in less than about two minutes. By controlling the ramp-up time, the annealing time and/or temperature and/or the ramp-down time, high performance silicon carbide power devices may be fabricated.
摘要翻译：碳化硅功率器件通过掩蔽碳化硅衬底的表面来限定衬底上的开口来制造，通过开口以通过开口将p型掺杂剂注入到碳化硅衬底中，所述注入能量和剂量形成深P型植入物，以及通过所述开口以注入能量和剂量将n型掺杂剂注入到所述碳化硅衬底中，所述能量和剂量相对于深P型植入物形成浅的n型植入物。深p型植入物和浅n型植入物在小于1650℃，但优选大于约1500°退火。退火优选发生约5分钟至约30分钟。从室温到退火温度的上升时间也被控制在小于约百分钟但大于约三十分钟。退火后的斜坡时间也可以通过将温度从退火温度降低到低于约1500℃，在少于约两分钟内来控制。通过控制升温时间，退火时间和/或温度和/或减速时间，可以制造高性能碳化硅功率器件。

22. 发明授权

US6107142A Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion 失效
标题翻译：通过注入和横向扩散制造碳化硅功率器件的自对准方法
公开(公告)号：US6107142A
公开(公告)日：2000-08-22
申请号：US93207
申请日：1998-06-08
申请人： Alexander Suvorov , John W. Palmour , Ranbir Singh
发明人： Alexander Suvorov , John W. Palmour , Ranbir Singh
IPC分类号： H01L21/04 , H01L21/225 , H01L21/265 , H01L21/336 , H01L29/12 , H01L29/24 , H01L29/78
CPC分类号： H01L29/7816 , H01L21/046 , H01L29/66068 , H01L29/7801 , H01L29/7802 , H01L29/1608 , Y10S438/931
摘要： Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed. Thereby, a p-base may be formed around an n-type source. Lateral and vertical power MOSFETs may be fabricated.
摘要翻译：通过在掩模中的开口将p型掺杂剂注入到碳化硅衬底中以形成深p型植入物来制造碳化硅功率器件。 N型掺杂剂通过掩模中相同的开口注入到碳化硅衬底中，以形成相对于p型植入物的浅n型植入物。然后在足以使深p型植入物横向扩散到围绕浅n型植入物的碳化硅衬底的表面而不将p型植入物垂直扩散到硅表面的温度和时间进行退火碳化物衬底通过浅的n型植入物。因此，可以通过离子注入来执行自对准的浅和深的植入物，并且可以通过退火形成良好控制的通道，其促进具有高扩散率的p型掺杂剂的显着扩散，而n型掺杂剂具有低的扩散性保持相对固定。由此，可以在n型源周围形成p基。可以制造横向和垂直功率MOSFET。

23. 发明授权

US08080441B2 Growing polygonal carbon from photoresist 有权
标题翻译：从光致抗蚀剂生长多边形碳
公开(公告)号：US08080441B2
公开(公告)日：2011-12-20
申请号：US12686066
申请日：2010-01-12
申请人： Alexander Suvorov
发明人： Alexander Suvorov
IPC分类号： H01L51/40
CPC分类号： H01L21/02378 , H01L21/02527 , H01L21/02612 , H01L21/02664 , H01L21/76256 , H01L29/1606 , H01L29/7781 , H01L29/78
摘要： A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.
摘要翻译：公开了一种从光致抗蚀剂和所得结构生长多边形碳的方法。本发明的实施例提供了通过激励半导体光致抗蚀剂来生产多边形碳（例如石墨烯）的方法。然后可以将多边形碳用于成品半导体器件中的导电路径，以替代碳化硅基底上的MOSFET器件中的沟道层，或者在衬底上形成的石墨烯或类似石墨烯的碳材料适合的任何其它目的。在一些实施方案中，光致抗蚀剂层在多边形碳层上形成多边形碳层和无定形碳层，并且去除无定形碳层以留下基材上的多边形碳。

24. 发明授权

US08049272B2 Transistors having implanted channel layers and methods of fabricating the same 有权
标题翻译：具有植入沟道层的晶体管及其制造方法
公开(公告)号：US08049272B2
公开(公告)日：2011-11-01
申请号：US11735799
申请日：2007-04-16
申请人： Jason P. Henning , Allan Ward , Alexander Suvorov
发明人： Jason P. Henning , Allan Ward , Alexander Suvorov
IPC分类号： H01L29/666 , H01L29/78
CPC分类号： H01L29/8128 , H01L29/1025 , H01L29/1608 , H01L29/2003 , H01L29/66848 , Y10T428/24612
摘要： A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming a MESFET include providing a layer of silicon carbide, forming spaced apart source and drain regions in the silicon carbide layer, implanting impurity atoms to form a channel region between the source and drain regions, annealing the implanted impurity atoms, and forming a gate contact on the silicon carbide layer.
摘要翻译： MESFET包括碳化硅层，碳化硅层中的间隔开的源极和漏极区域，位于源极和漏极区域之间的碳化硅层内并掺杂有注入的掺杂剂的沟道区域，以及碳化硅层上的栅极接触。形成MESFET的方法包括提供碳化硅层，在碳化硅层中形成间隔开的源极和漏极区域，注入杂质原子以在源极和漏极区域之间形成沟道区域，退火注入的杂质原子，并形成栅极接触在碳化硅层上。

25. 发明授权

US08008637B2 High-temperature ion implantation apparatus and methods of fabricating semiconductor devices using high-temperature ion implantation 有权
标题翻译：高温离子注入装置及使用高温离子注入制造半导体器件的方法
公开(公告)号：US08008637B2
公开(公告)日：2011-08-30
申请号：US12422826
申请日：2009-04-13
申请人： Alexander Suvorov
发明人： Alexander Suvorov
IPC分类号： H01J37/317 , H01J37/20 , H01L21/265 , H01L21/425
CPC分类号： H01L21/67213 , Y10T16/469 , Y10T16/4707
摘要： A semiconductor device fabrication apparatus includes a load lock chamber, a loading assembly in the load lock chamber, and an ion implantation target chamber that is hermetically connected to the load lock chamber. The load lock chamber is configured to store a plurality of wafer plates. Each wafer plate respectively includes at least one semiconductor wafer thereon. The ion implantation target chamber is configured to implant an ion species into a semiconductor wafer on a currently loaded wafer plate. The loading assembly is also configured to load a next one of the plurality of wafer plates from the load lock chamber into the ion implantation target chamber. The loading assembly may be configured to load the next wafer plate from the load lock chamber into the ion implantation target chamber while substantially maintaining a current temperature within the ion implantation target chamber and/or without depressurizing the ion implantation target chamber. Related methods and devices are also discussed.
摘要翻译：半导体器件制造装置包括负载锁定室，负载锁定室中的装载组件和气密地连接到负载锁定室的离子注入目标室。负载锁定室被配置为存储多个晶片板。每个晶片板分别包括至少一个半导体晶片。离子注入靶室被配置为将离子物质注入到当前装载的晶片板上的半导体晶片中。装载组件还构造成将多个晶片板中的下一个从负载锁定室装载到离子注入目标室中。加载组件可以被配置为将下一个晶片板从负载锁定室加载到离子注入靶室中，同时基本上保持离子注入靶室内的当前温度和/或不使离子注入靶室减压。还讨论了相关的方法和设备。

26. 发明授权

US07592634B2 LED fabrication via ion implant isolation 有权
标题翻译：通过离子注入隔离制造LED
公开(公告)号：US07592634B2
公开(公告)日：2009-09-22
申请号：US11154619
申请日：2005-06-16
申请人： Yifeng Wu , Gerald H. Negley , David B. Slater, Jr. , Valeri F. Tsvetkov , Alexander Suvorov
发明人： Yifeng Wu , Gerald H. Negley , David B. Slater, Jr. , Valeri F. Tsvetkov , Alexander Suvorov
IPC分类号： H01L33/00
CPC分类号： H01L33/32 , H01L33/305
摘要： A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.
摘要翻译：半导体发光二极管包括半导体衬底，衬底上的n型III族氮化物的外延层，n型外延层上的III族氮化物的p型外延层，并与n型外延层形成pn结，型层和n型外延层上的电阻性氮化镓区，并且邻近p型外延层，用于电隔离pn结的部分。在p型外延层上形成金属接触层。在公开的方法实施例中，通过在p型外延区上形成注入掩模并将离子注入到p型外延区的一部分中以形成半绝缘的p型外延区的部分来形成电阻性氮化镓边界。可以使用光致抗蚀剂掩模或足够厚的金属层作为植入物掩模。

27. 发明申请

US20070292999A1 Transistors Having Implanted Channel Layers and Methods of Fabricating the Same 有权
标题翻译：具有嵌入通道层的晶体管及其制造方法
公开(公告)号：US20070292999A1
公开(公告)日：2007-12-20
申请号：US11735799
申请日：2007-04-16
申请人： Jason Henning , Allan Ward , Alexander Suvorov
发明人： Jason Henning , Allan Ward , Alexander Suvorov
IPC分类号： H01L21/338 , H01L31/112
CPC分类号： H01L29/8128 , H01L29/1025 , H01L29/1608 , H01L29/2003 , H01L29/66848 , Y10T428/24612
摘要： A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming a MESFET include providing a layer of silicon carbide, forming spaced apart source and drain regions in the silicon carbide layer, implanting impurity atoms to form a channel region between the source and drain regions, annealing the implanted impurity atoms, and forming a gate contact on the silicon carbide layer.
摘要翻译： MESFET包括碳化硅层，碳化硅层中的间隔开的源极和漏极区域，位于源极和漏极区域之间的碳化硅层内并掺杂有注入的掺杂剂的沟道区域，以及碳化硅层上的栅极接触。形成MESFET的方法包括提供碳化硅层，在碳化硅层中形成间隔开的源极和漏极区域，注入杂质原子以在源极和漏极区域之间形成沟道区域，退火注入的杂质原子，并形成栅极接触在碳化硅层上。

28. 发明申请

US20060108595A9 LED fabrication via ion implant isolation 有权
公开(公告)号：US20060108595A9
公开(公告)日：2006-05-25
申请号：US10840463
申请日：2004-05-06
申请人： Yifeng Wu , Gerald Negley , David Slater , Valeri Tsvetkov , Alexander Suvorov
发明人： Yifeng Wu , Gerald Negley , David Slater , Valeri Tsvetkov , Alexander Suvorov
IPC分类号： H01L21/00 , H01L33/00
CPC分类号： H01L33/145 , H01L24/73 , H01L33/0095 , H01L33/025 , H01L33/32 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , Y02P80/30 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.

29. 发明授权

US06995398B2 Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices 有权
标题翻译：处理碳化硅衬底以改善外延沉积以及所得结构和器件的方法
公开(公告)号：US06995398B2
公开(公告)日：2006-02-07
申请号：US10709780
申请日：2004-05-27
申请人： Davis Andrew McClure , Alexander Suvorov , John A. Edmond , David B. Slater, Jr.
发明人： Davis Andrew McClure , Alexander Suvorov , John A. Edmond , David B. Slater, Jr.
IPC分类号： H01L31/0312
CPC分类号： H01L33/007 , H01L21/02378 , H01L21/02658 , H01L21/046 , H01L21/2003 , H01L29/6606 , H01L33/0062 , Y10S438/931
摘要： A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
摘要翻译：公开了一种用于处理碳化硅衬底以改进其上的外延沉积并用作制造诸如发光二极管的器件中的前体的方法。该方法包括以下步骤：将第一导电类型的掺杂剂原子注入具有与一种或多种预定掺杂剂浓度的注入离子相同的导电类型的导电碳化硅晶片的第一表面，并且注入能量以形成掺杂剂分布，退火所述植入的晶片，以及在所述晶片的植入的第一表面上生长外延层。

30. 发明授权

US06884644B1 Low temperature formation of backside ohmic contacts for vertical devices 有权
标题翻译：低温形成用于垂直器件的背面欧姆接触
公开(公告)号：US06884644B1
公开(公告)日：2005-04-26
申请号：US09787189
申请日：1999-09-16
申请人： David B. Slater, Jr. , Alexander Suvorov
发明人： David B. Slater, Jr. , Alexander Suvorov
IPC分类号： H01L21/04 , H01L31/0224 , H01L33/00 , H01L33/34 , H01L33/36 , H01L21/00
CPC分类号： H01L31/022408 , H01L21/0485 , H01L33/0095 , H01L33/34 , H01L33/36
摘要： The invention comprises a method for forming a metal-semiconductor ohmic contact (18) for use in a semiconductor device (10) having a plurality of epitaxial layers (14a-c) wherein the ohmic contact (18) is preferably formed after deposition of the epitaxial layers (14a-c). The invention also comprises a semiconductor device comprising a plurality of epitaxial layers and an ohmic contact.
摘要翻译：本发明包括一种形成用于具有多个外延层（14ac）的半导体器件（10）的金属 - 半导体欧姆接触（18）的方法，其中欧姆接触（18）优选在沉积外延层层（14 ac）。本发明还包括包括多个外延层和欧姆接触的半导体器件。

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