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21. 发明授权

US5678301A Method for forming an interconnect for testing unpackaged semiconductor dice 失效
标题翻译：用于形成用于测试未封装的半导体晶片的互连的方法
公开(公告)号：US5678301A
公开(公告)日：1997-10-21
申请号：US563509
申请日：1995-11-27
申请人： Derek Gochnour , Warren M. Farnworth
发明人： Derek Gochnour , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/42 , H01R43/00
CPC分类号： H01L23/49838 , G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R1/06761 , G01R3/00 , G01R31/2831 , G01R31/2863 , H01L2224/16145 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/49121 , Y10T29/49144 , Y10T29/49149
摘要： A method for forming an interconnect for establishing electrical communication with a semiconductor die is provided. The method includes: providing a microbump tape and then mounting the tape to a substrate with a compliant layer therebetween. The microbump tape includes an insulating film having a pattern of microbump contact members corresponding to a pattern of bond pads on the die. The compliant layer can be formed of a curable adhesive such as a silicone elastomer. A coupon containing a plurality of microbump tapes can be mounted to a substrate wafer which can then be singulated to form a plurality of interconnects. The interconnects can be used with a testing apparatus for testing unpackaged semiconductor dice.
摘要翻译：提供一种用于形成用于与半导体管芯建立电连通的互连的方法。该方法包括：提供微型胶带，然后将胶带安装到其上具有柔顺层的基材上。微型胶带包括具有对应于模具上的接合焊盘图案的微型块接触部件图案的绝缘膜。柔性层可以由可固化粘合剂如硅氧烷弹性体形成。可以将包含多个微型带的试样安装到基板晶片上，然后可以将其分离以形成多个互连。互连可用于测试未封装的半导体裸片的测试设备。

22. 发明授权

US07011532B2 Spring element for use in an apparatus for attaching to a semiconductor and a method of making 失效
公开(公告)号：US07011532B2
公开(公告)日：2006-03-14
申请号：US11122626
申请日：2005-05-05
申请人： David R. Hembree , Salman Akram , Derek Gochnour
发明人： David R. Hembree , Salman Akram , Derek Gochnour
IPC分类号： H01R12/00
CPC分类号： G01R1/0466 , Y10T29/49117 , Y10T29/49147 , Y10T29/49149 , Y10T29/49153 , Y10T29/53209 , Y10T29/5323
摘要： A spring element used in a temporary package for testing semiconductors is provided. The spring element is compressed so as to press the semiconductor, either in the form of a bare semiconductor die or as part of a package, against an interconnect structure. The spring element is configured so that it provides sufficient pressure to keep the contacts on the semiconductor in electrical contact with the interconnect structure. Material is added and/or removed from the spring element so that it has the desired modulus of elasticity. The shape of the spring element may also be varied to change the modulus of elasticity, the spring constant, and the force transfer capabilities of the spring element.

23. 发明授权

US06396291B1 Method for testing semiconductor components 失效
标题翻译：半导体元件测试方法
公开(公告)号：US06396291B1
公开(公告)日：2002-05-28
申请号：US09723101
申请日：2000-11-28
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

24. 发明授权

US06351034B1 Clip chip carrier 失效
标题翻译：剪辑芯片载体
公开(公告)号：US06351034B1
公开(公告)日：2002-02-26
申请号：US09088605
申请日：1998-06-01
申请人： Warren M. Farnworth , Derek Gochnour , Alan Wood
发明人： Warren M. Farnworth , Derek Gochnour , Alan Wood
IPC分类号： H01L2334
CPC分类号： H01L24/75 , H01L23/32 , H01L24/72 , H01L2224/16225 , H01L2224/73251 , H01L2224/75315 , H01L2224/81901 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/16 , H01L2224/72 , H01L2224/0401
摘要： A chip carrier for temporarily connecting a semiconductor chip to a testing device. The chip carrier includes a substrate having a first set of contact points for electrically engaging the testing device and a second set of contact points to be connected with the contact elements of the semiconductor chip. The semiconductor chip is disposed on the substrate and is substantially covered by a cover member. One or more clips are in contact with the cover member and are used to secure the semiconductor chip in position. The clips have a first member removably attached to the substrate and a second member separated from the first member and in contact with the cover member. As the second member is displaced from an unstressed position, a force is generated by the clip and transferred to the cover member and the semiconductor chip. The chip carrier reliably secures the semiconductor chip while occupying a relatively small space over the semiconductor chip.
摘要翻译：用于将半导体芯片临时连接到测试装置的芯片载体。芯片载体包括具有用于电耦合测试装置的第一组接触点和要与半导体芯片的接触元件连接的第二组接触点的基板。半导体芯片设置在基板上并且基本上被盖构件覆盖。一个或多个夹子与盖构件接触并用于将半导体芯片固定就位。夹子具有可移除地附接到基底的第一构件和与第一构件分离并与盖构件接触的第二构件。当第二构件从非受压位置移位时，夹子产生力并将其传递到盖构件和半导体芯片。芯片载体在半导体芯片占据相对较小的空间的同时可靠地固定半导体芯片。

25. 发明授权

US06307394B1 Test carrier with variable force applying mechanism for testing semiconductor components 失效
公开(公告)号：US06307394B1
公开(公告)日：2001-10-23
申请号：US09231347
申请日：1999-01-13
申请人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
发明人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/0466
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

26. 发明授权

US06297660B2 Test carrier with variable force applying mechanism for testing semiconductor components 失效
公开(公告)号：US06297660B2
公开(公告)日：2001-10-02
申请号：US09734514
申请日：2000-12-12
申请人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
发明人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/0466
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

27. 发明授权

US06255840B1 Semiconductor package with wire bond protective member 有权
标题翻译：半导体封装带引线键合保护元件
公开(公告)号：US06255840B1
公开(公告)日：2001-07-03
申请号：US09304941
申请日：1999-05-04
申请人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
发明人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01079 , H01L2924/16195 , H01L2924/00014
摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.
摘要翻译：提供了一种用于测试半导体晶片的封装，系统和方法。该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

28. 发明授权

US06242931B1 Flexible semiconductor interconnect fabricated by backside thinning 有权
公开(公告)号：US06242931B1
公开(公告)日：2001-06-05
申请号：US09756626
申请日：2001-01-08
申请人： David R. Hembree , Derek Gochnour
发明人： David R. Hembree , Derek Gochnour
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R1/06738 , G01R1/06761 , H01L2224/16237 , H01L2224/8114 , H01R13/24 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208 , Y10T29/49224
摘要： An interconnect for testing semiconductor components includes a thinned substrate, and first contacts on the substrate for electrically engaging second contacts on the components. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. The thinned substrate has a thickness that is substantially less than a thickness of the components being tested. The thinned substrate can flex upon application of a biasing force by the testing apparatus, permitting the first contacts to move in the z-direction to accommodate variations in the planarity of the second contacts. For fabricating the interconnect, the first contacts are formed on the substrate, and then covered with a protective mask. With the mask in place, the substrate can be thinned by grinding, chemical mechanical planarization, or alternately by etching a backside of the substrate. Other process steps such as via formation and backside metallization can also be performed with the protective mask in place. The protective mask can then be removed, and the thinned substrate attached to a rigid substrate, or base, using a compliant polymer layer.

29. 发明授权

US6072326A System for testing semiconductor components 失效
标题翻译：半导体元件测试系统
公开(公告)号：US6072326A
公开(公告)日：2000-06-06
申请号：US916434
申请日：1997-08-22
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

30. 发明授权

US6057597A Semiconductor package with pre-fabricated cover 有权
标题翻译：具有预制盖的半导体封装
公开(公告)号：US6057597A
公开(公告)日：2000-05-02
申请号：US172451
申请日：1998-10-14
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L23/12
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

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