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    • 23. 发明授权
    • Serial and parallel scan technique for improved testing of systolic
arrays
    • 串并行扫描技术,用于改善收缩阵列的测试
    • US5130989A
    • 1992-07-14
    • US494016
    • 1990-03-15
    • Daryl E. AndersonRalph H. LanhamNeal C. Jaarsma
    • Daryl E. AndersonRalph H. LanhamNeal C. Jaarsma
    • G01R31/317G01R31/28G01R31/3185G06F11/22G11C29/00G11C29/02G11C29/56
    • G01R31/318516
    • A method for testing a systolic array in which a plurality of sequential registers is each connected to the rest by an intervening logic component. Each register includes a plurality of memory elements. Each register can be enabled to act as a latch register whereby digital data is loaded into an output therefrom in parallel or as a shift register whereby digital data is shifted sequentially in each register from one memory element to the next adjacent memory element. A test vector consisting of a preselected string of digital data is shifted in parallel into each of the registers. The test vector in each register is loaded into the associated logic component which operates on the vector and stores the data in the next adjacent register. The resulting data is serially clocked from each register onto unique bus nodes and examined in parallel to determine whether or not the expected result was obtained.
    • 一种用于测试心脏阵列的方法,其中多个顺序寄存器各自通过中间的逻辑组件连接到其余的。 每个寄存器包括多个存储元件。 每个寄存器可以被用作锁存寄存器,由此数字数据被并行地加载到其输出中,或者作为移位寄存器,由此数字数据在每个寄存器中从一个存储元件顺序地移位到下一个相邻的存储元件。 由预选的数字数据串组成的测试向量并行移位到每个寄存器中。 每个寄存器中的测试向量被加载到相关联的逻辑组件中,该组件对向量进行操作并将数据存储在下一个相邻寄存器中。 所得到的数据从每个寄存器被串行计时到独特的总线节点上并行检查以确定是否获得预期的结果。