会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 28. 发明授权
    • Input and output circuit and method of operation thereof
    • 输入输出电路及其操作方法
    • US07224198B2
    • 2007-05-29
    • US11226564
    • 2005-09-14
    • Jeong-Seok ChaeYoon-Jay ChoHyo-Jin Kim
    • Jeong-Seok ChaeYoon-Jay ChoHyo-Jin Kim
    • G06F1/04
    • G01R19/16542H02H7/18
    • An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.
    • 输入和输出电路包括公共输入和输出节点,异常电压检测器和时钟发生电路。 公共输入和输出节点用作正常操作模式的输出节点,并在作为输入节点输入到公共输入和输出节点的测试操作模式中用作输入节点。 异常电压检测器基于在测试操作模式下检测公共输入和输出节点处的异常电压电平而产生异常电压信号。 时钟发生电路在正常操作模式下向公共输入和输出节点输出第一时钟信号,并响应于测试操作模式中的异常电压信号将外部电路输出第二时钟信号。 因此,可以减少用于测试输入和输出电路的时间和费用。
    • 29. 发明申请
    • Input and output circuit and method of operation thereof
    • 输入输出电路及其操作方法
    • US20060055376A1
    • 2006-03-16
    • US11226564
    • 2005-09-14
    • Jeong-Seok ChaeYoon-Jay ChoHyo-Jin Kim
    • Jeong-Seok ChaeYoon-Jay ChoHyo-Jin Kim
    • H02J7/00
    • G01R19/16542H02H7/18
    • An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.
    • 输入和输出电路包括公共输入和输出节点,异常电压检测器和时钟发生电路。 公共输入和输出节点用作正常操作模式的输出节点,并在作为输入节点输入到公共输入和输出节点的测试操作模式中使用。 异常电压检测器基于在测试操作模式下检测公共输入和输出节点处的异常电压电平而产生异常电压信号。 时钟发生电路在正常操作模式下向公共输入和输出节点输出第一时钟信号,并响应于测试操作模式中的异常电压信号将外部电路输出第二时钟信号。 因此,可以减少用于测试输入和输出电路的时间和费用。