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    • 21. 发明申请
    • Test apparatus and test method
    • 试验装置及试验方法
    • US20100308856A1
    • 2010-12-09
    • US12605965
    • 2009-10-26
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • G01R31/26
    • G01R29/027G01R31/3004G01R31/31703G01R31/31932
    • Provided is a test apparatus for testing a device under test, including: a level comparing section that receives a signal under test output from the device under test and outputs a logical value, the logical value indicating a comparison result obtained by comparing a signal level of the signal under test with preset first threshold and second threshold; an acquiring section that acquires the logical value output from the level comparing section, according to a strobe signal supplied thereto; an expected value comparing circuit that determines whether the logical value acquired by the acquiring section corresponds to a preset expected value; and a threshold control section that sets an upper limit and a lower limit of a voltage of the eye mask to the level comparing section as the first threshold and the second threshold, when an eye mask test is performed for determining whether an eye opening of the signal under test is larger than a predefined eye mask.
    • 提供了一种用于测试被测设备的测试装置,包括:电平比较部分,接收被测器件输出的信号,并输出逻辑值,逻辑值表示通过比较信号电平 被测信号具有预设的第一阈值和第二阈值; 获取部分,根据提供给其的选通信号,获取从电平比较部分输出的逻辑值; 预测值比较电路,其确定由所述获取部获取的逻辑值是否对应于预设期望值; 以及阈值控制部,其将所述眼罩的电压的上限和下限设定为所述电平比较部作为所述第一阈值和所述第二阈值,当进行用于确定所述眼图的眼睛开度 被测信号大于预定义的眼罩。
    • 22. 发明申请
    • CLOCK DATA RECOVERY CIRCUIT AND METHOD
    • 时钟数据恢复电路和方法
    • US20100090737A1
    • 2010-04-15
    • US12532132
    • 2008-03-18
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • H03L7/00
    • H04L7/033G01R31/31727G01R31/31937H03L7/0812H04L7/0037
    • A change-point detection circuit 16 extracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.
    • 变化点检测电路16从串行数据,输入数据中提取时钟信号。 可变延迟电路根据具有预定频率的参考信号的延迟控制信号提供延迟,使得参考信号的相位基于初始延迟而偏移。 输入锁存电路通过使用可变延迟电路的输出信号作为选通信号来锁存内部串行数据。 相位比较器将时钟信号和选通信号的频率相互匹配,并根据两个信号之间的相位差产生相位差数据。 环路滤波器对相位比较器产生的相位差数据进行积分,并将其作为延迟控制信号输出。 相移量获取单元基于延迟控制信号获取相移量,相移量基于由可变延迟电路提供给参考信号的初始延迟。
    • 23. 发明授权
    • Transmission system, signal receiver, test apparatus and test head
    • 传输系统,信号接收器,测试仪器和测试头
    • US07555038B2
    • 2009-06-30
    • US11296806
    • 2005-12-07
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • H04B3/46
    • H04L7/0012G01R31/31922H03L7/07H03L7/0812H03L7/087H04L7/0037H04L7/0337
    • A transmission system for transmitting a transmission signal, includes a section for outputting a periodic clock having a preset period, a section for transmitting the transmission signal in synchronism with the periodic clock, and a section for receiving the transmission signal transmitted from the transmitting section. The receiving section includes a section for generating a data synchronizing clock synchronized with variation of values of sampling data, section for detecting a phase difference between the periodic clock and the data synchronizing clock, and a section for generating a phase variable clock obtained by varying phase of the periodic clock so that a variable phase difference which is a phase difference between the phase variable clock and the data synchronizing clock becomes an amount set in advance.
    • 用于发送发送信号的发送系统包括用于输出具有预设周期的周期性时钟的部分,用于与周期性时钟同步发送发送信号的部分,以及用于接收从发送部发送的发送信号的部分。 接收部分包括用于产生与采样数据的值的变化同步的数据同步时钟的部分,用于检测周期性时钟和数据同步时钟之间的相位差的部分,以及用于产生通过改变相位而获得的相位可变时钟的部分 使得作为相位可变时钟和数据同步时钟之间的相位差的可变相位差成为预先设定的量。
    • 27. 发明申请
    • Oscillator, frequency multiplier, and test apparatus
    • 振荡器,倍频器和测试仪器
    • US20060261903A1
    • 2006-11-23
    • US11441796
    • 2006-05-26
    • Daisuke WatanabeToshiyuki Okayasu
    • Daisuke WatanabeToshiyuki Okayasu
    • H03B27/00
    • G01R31/31922H03K5/133H03K2005/00019H03L7/0812
    • There is provided an oscillator for generating an oscillating signal having desired frequency, having a reference oscillating section for generating a reference signal having predetermined frequency, a plurality of first variable delay circuits, connected in cascade, for receiving the reference signal and outputting the received reference signal by sequentially delaying by almost equal values of delay, a phase comparing section for comparing phase of the reference signal generated by the reference oscillating section with phase of a delay signal outputted out of a final stage of the plurality of first variable delay circuits, a delay control section for controlling a value of delay of the plurality of first variable delay circuits so that the phase of the reference signal becomes almost equal to the phase of the delay signal outputted out of the final stage of the plurality of first variable delay circuits and a frequency adding circuit for generating the oscillating signal in which edges of the respective input signals are combined by logically operating the input signals inputted to the respective first variable delay circuits.
    • 提供了一种用于产生具有期望频率的振荡信号的振荡器,具有用于产生具有预定频率的参考信号的参考振荡部分,级联连接的多个第一可变延迟电路,用于接收参考信号并输出​​接收到的参考 通过依次延迟几乎相等的延迟值的相位比较部分,用于将参考振荡部分产生的参考信号的相位与多个第一可变延迟电路的最后一级输出的延迟信号的相位进行比较的相位比较部分, 延迟控制部分,用于控制多个第一可变延迟电路的延迟值,使得参考信号的相位变得几乎等于从多个第一可变延迟电路的最后一级输出的延迟信号的相位;以及 用于产生振荡信号的频率添加电路, 通过对输入到各个第一可变延迟电路的输入信号进行逻辑运算来组合各个输入信号的ges。