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21. 发明授权

US06207540B1 Method for manufacturing high performance MOSFET device with raised source and drain 失效
标题翻译：用于制造具有升高的源极和漏极的高性能MOSFET器件的方法
公开(公告)号：US06207540B1
公开(公告)日：2001-03-27
申请号：US09379940
申请日：1999-08-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L2138
CPC分类号： H01L29/66613 , H01L21/2255 , H01L29/66621 , H01L29/7834
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

22. 发明授权

US6107133A Method for making a five square vertical DRAM cell 失效
标题翻译：制造五平方垂直DRAM单元的方法
公开(公告)号：US6107133A
公开(公告)日：2000-08-22
申请号：US85965
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： Five square dynamic random access memory (DRAM) cell is prepared with a vertical transfer device with long channel length. In this construction, channel length is not affected by cell size scaling requirements.
摘要翻译：使用具有长通道长度的垂直传送装置制备五平方动态随机存取存储器（DRAM）单元。在这种结构中，通道长度不受单元尺寸缩放要求的影响。

23. 发明授权

US07521776B2 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
标题翻译：使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
公开(公告)号：US07521776B2
公开(公告)日：2009-04-21
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

24. 发明授权

US07081387B2 Damascene gate multi-mesa MOSFET 失效
标题翻译：镶嵌门多台面MOSFET
公开(公告)号：US07081387B2
公开(公告)日：2006-07-25
申请号：US10918949
申请日：2004-08-16
申请人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
发明人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
摘要翻译：公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法，例如气相掺杂或等离子体掺杂时。所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。

25. 发明授权

US06818952B2 Damascene gate multi-mesa MOSFET 有权
公开(公告)号：US06818952B2
公开(公告)日：2004-11-16
申请号：US10262190
申请日：2002-10-01
申请人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
发明人： Toshiharu Furukawa , Jack A. Mandelman , Byeongju Park
IPC分类号： H01L2701
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66795 , H01L29/78621 , H01L29/78636
摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

26. 发明授权

US06323082B1 Process for making a DRAM cell with three-sided gate transfer 失效
标题翻译：用于制造具有三面栅极转移的DRAM单元的工艺
公开(公告)号：US06323082B1
公开(公告)日：2001-11-27
申请号：US09565504
申请日：2000-05-05
申请人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
发明人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/7851 , Y10S257/906 , Y10S438/947
摘要： A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.
摘要翻译： DRAM装置和制造装置的过程。 DRAM装置包括通过由字线控制的传送装置耦合到信号存储节点的位线。转印装置包括具有第一端，与第一端相对的第二端，顶部，第一侧和与第一侧相对的第二侧的台面结构。位线扩散区域将台面结构的第一端耦合到位线接触。存储节点扩散区将台面结构的第二端耦合到信号存储节点。字线通过形成在台面结构的第一面，第二面和顶部上的栅极来控制形成在台面结构中的通道。台面结构的亚最小宽度允许容易地实现完全耗尽，导致通道中的体积反转。

27. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

28. 发明授权

US6121651A Dram cell with three-sided-gate transfer device 失效
标题翻译：具有三边门转移装置的电池
公开(公告)号：US6121651A
公开(公告)日：2000-09-19
申请号：US126412
申请日：1998-07-30
申请人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
发明人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L27/10829 , H01L29/7851 , Y10S257/906 , Y10S438/947
摘要： A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.
摘要翻译： DRAM装置和制造装置的过程。 DRAM装置包括通过由字线控制的传送装置耦合到信号存储节点的位线。转印装置包括具有第一端，与第一端相对的第二端，顶部，第一侧和与第一侧相对的第二侧的台面结构。位线扩散区域将台面结构的第一端耦合到位线接触。存储节点扩散区将台面结构的第二端耦合到信号存储节点。字线通过形成在台面结构的第一面，第二面和顶部上的栅极来控制形成在台面结构中的通道。台面结构的亚最小宽度允许容易地实现完全耗尽，导致通道中的体积反转。

29. 发明授权

US6037194A Method for making a DRAM cell with grooved transfer device 失效
标题翻译：制造具有槽式转印装置的DRAM单元的方法
公开(公告)号：US6037194A
公开(公告)日：2000-03-14
申请号：US281136
申请日：1999-03-29
申请人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
发明人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
IPC分类号： H01L21/8242 , H01L21/339
CPC分类号： H01L27/10876 , H01L27/10861 , H01L27/10891
摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.
摘要翻译：公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

30. 发明授权

US5949700A Five square vertical dynamic random access memory cell 失效
标题翻译：五平方垂直动态随机存取存储单元
公开(公告)号：US5949700A
公开(公告)日：1999-09-07
申请号：US165503
申请日：1998-10-02
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10864 , H01L27/10841
摘要： Five square dynamic random access memory (DRAM) cell is prepared with a vertical transfer device with long channel length. In this construction, channel length is not affected by cell size scaling requirements.
摘要翻译：使用具有长通道长度的垂直传送装置制备五平方动态随机存取存储器（DRAM）单元。在这种结构中，通道长度不受单元尺寸缩放要求的影响。

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