专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07442621B2 Semiconductor process for forming stress absorbent shallow trench isolation structures 有权
标题翻译：用于形成应力吸收性浅沟槽隔离结构的半导体工艺
公开(公告)号：US07442621B2
公开(公告)日：2008-10-28
申请号：US10996319
申请日：2004-11-22
申请人： Marius K. Orlowski , Mark C. Foisy , Olubunmi O. Adetutu
发明人： Marius K. Orlowski , Mark C. Foisy , Olubunmi O. Adetutu
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译：半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

22. 发明授权

US07435646B2 Method for forming floating gates within NVM process 有权
标题翻译：在NVM过程中形成浮动门的方法
公开(公告)号：US07435646B2
公开(公告)日：2008-10-14
申请号：US11208670
申请日：2005-08-22
申请人： Jeffrey W. Thomas , Olubunmi O. Adetutu
发明人： Jeffrey W. Thomas , Olubunmi O. Adetutu
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.
摘要翻译：半导体工艺和设备包括通过在半导体结构（10）上沉积氮化物层（20）来形成半导体器件，图案化和蚀刻氮化物层以形成图案化氮化物层（42,44），沉积多晶硅层（62），用CMP工艺平坦化多晶硅层，以去除图案化的介电层（42,44）上方的多晶硅层（62）的任何部分，然后去除图案化的氮化物层（42,44），由此限定一个或更多个可用作浮动栅极，晶体管栅极，位线或任何其它半导体器件特征的多晶硅特征（72,74,76）。

23. 发明授权

US07303983B2 ALD gate electrode 有权
标题翻译： ALD栅电极
公开(公告)号：US07303983B2
公开(公告)日：2007-12-04
申请号：US11331763
申请日：2006-01-13
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , James K. Schaeffer
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , James K. Schaeffer
IPC分类号： H01L21/3205
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.
摘要翻译：一种半导体工艺和装置，通过在栅介质层（11）上形成第一导电层（22）制造金属栅电极，在第一导电层上形成过渡层（32），使用原子层沉积工艺，其中非晶化随着形成过渡层，材料越来越多地加入，在过渡层上形成覆盖导电层（44），然后选择性地蚀刻覆盖导电层，过渡层和第一导电层，从而形成蚀刻栅叠层（52）。通过用原子层沉积工艺形成过渡层（32），其中非晶化材料（例如硅，碳或氮）越来越多地被加入，过渡层（32）被构造成具有较低的区域（例如，31， 33）和具有阻挡硅扩散的非晶结构的上部区域（例如，37,39）。

24. 发明授权

US07179700B2 Semiconductor device with low resistance contacts 有权
标题翻译：具有低电阻触点的半导体器件
公开(公告)号：US07179700B2
公开(公告)日：2007-02-20
申请号：US10895553
申请日：2004-07-21
申请人： Olubunmi O. Adetutu , William J. Taylor, Jr.
发明人： Olubunmi O. Adetutu , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/456
摘要： An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to the P work function of 5.2 electron volts, and the N-type source/drain contacts of the N channel transistors have a silicide that is close to the N work function of 4.1 electron volts. This provides for a lower resistance at the interface between these source/drain contact regions and the corresponding silicide. These suicides with differing work functions are achieved with implants as needed. For example, for N-type source/drain contacts and a base metal of cobalt, titanium, or nickel, the implanted material is platinum and/or iridium. For the P-type, the implanted material is erbium, yttrium, dysprosium, gadolinium, hafnium, or holmium.
摘要翻译： N沟道晶体管和P沟道晶体管的源极/漏极接触不同的自杀，以提供低电阻触点。选择硅化物以提供工作功能的良好匹配。 P沟道晶体管的P型源极/漏极触点具有接近5.2电子伏特的P功函数的硅化物，并且N沟道晶体管的N型源极/漏极触点具有接近于 4.1电子伏特的N工作功能。这提供了在这些源极/漏极接触区域和相应的硅化物之间的界面处的较低电阻。具有不同工作功能的这些自杀根据需要用植入物实现。例如，对于N型源极/漏极触点和钴，钛或镍的母体金属，植入的材料是铂和/或铱。对于P型，植入的材料是铒，钇，镝，钆，铪或钬。

25. 发明授权

US06987063B2 Method to reduce impurity elements during semiconductor film deposition 有权
标题翻译：在半导体膜沉积期间减少杂质元素的方法
公开(公告)号：US06987063B2
公开(公告)日：2006-01-17
申请号：US10865452
申请日：2004-06-10
申请人： Olubunmi O. Adetutu , James K. Schaeffer , Dina H. Triyoso
发明人： Olubunmi O. Adetutu , James K. Schaeffer , Dina H. Triyoso
IPC分类号： H01L21/44
CPC分类号： C23C14/0005 , C23C16/4401 , C23C16/56 , H01L21/3141 , H01L21/31604 , H01L21/31645
摘要： A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.
摘要翻译：通过避免包含降低金属介电常数的污染元素的方法，形成具有高介电常数的含金属的半导体层。含金属的半导体层形成在室内的基板上。引入前体以沉积至少一部分含金属的半导体层。前体含有一种或多种元素，如果允许沉积在含金属的层中，则会成为杂质元素。反应气体用于通过从由前体引入室中的含金属层去除杂质元素来净化含金属层。

26. 发明授权

US08404594B2 Reverse ALD 有权
标题翻译：反向ALD
公开(公告)号：US08404594B2
公开(公告)日：2013-03-26
申请号：US11139765
申请日：2005-05-27
申请人： Dina H. Triyoso , Olubunmi O. Adetutu
发明人： Dina H. Triyoso , Olubunmi O. Adetutu
IPC分类号： C23F1/00 , H01L21/461 , H01L21/302 , B44C1/22
CPC分类号： H01L21/0228 , H01L21/02142 , H01L21/02175 , H01L21/265 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/3141 , H01L21/31645 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.
摘要翻译：半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅电极（151）并且形成第二栅极电极（161）至少形成第一栅极电极（151,161）与第一栅极电介质（121）不同的第二高k栅极电介质（122）。可以通过沉积和选择性蚀刻高k电介质材料的初始层（例如14）来形成高k栅极电介质层（121,122）之一或两者。沉积时，初始层（14）具有暴露表面（18）和初始预定晶体结构。通过改变暴露的薄表面层中的初始晶体结构，准备初始层（14）的暴露的薄表面层（20）用于蚀刻。暴露的薄表面层中的改性晶体结构可以通过施加选择性蚀刻如HF或HCl来去除。

27. 发明授权

US08030220B2 Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权
标题翻译：用于增强含金属层成核的半导体表面的等离子体处理
公开(公告)号：US08030220B2
公开(公告)日：2011-10-04
申请号：US12579072
申请日：2009-10-14
申请人： Dina H. Triyoso , Olubunmi O. Adetutu
发明人： Dina H. Triyoso , Olubunmi O. Adetutu
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译：提供一种形成电介质层的方法。该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为范围为1到60秒。该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。

28. 发明授权

US07618902B2 Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权
标题翻译：用于增强含金属层成核的半导体表面的等离子体处理
公开(公告)号：US07618902B2
公开(公告)日：2009-11-17
申请号：US11290320
申请日：2005-11-30
申请人： Dina H. Triyoso , Olubunmi O. Adetutu
发明人： Dina H. Triyoso , Olubunmi O. Adetutu
IPC分类号： H01L21/31 , H01L21/469 , H01L21/336
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译：提供一种形成电介质层的方法。该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为范围为1到60秒。该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。

29. 发明授权

US07579282B2 Method for removing metal foot during high-k dielectric/metal gate etching 有权
标题翻译：在高k电介质/金属栅极蚀刻期间去除金属脚的方法
公开(公告)号：US07579282B2
公开(公告)日：2009-08-25
申请号：US11331786
申请日：2006-01-13
申请人： Shahid Rauf , Olubunmi O. Adetutu , Eric D. Luckowski , Peter L. G. Ventzek
发明人： Shahid Rauf , Olubunmi O. Adetutu , Eric D. Luckowski , Peter L. G. Ventzek
IPC分类号： H01L21/285 , H01L21/3065
CPC分类号： H01L21/02071 , H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).
摘要翻译：金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82））。接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95）（80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。

30. 发明申请

US20080254617A1 Void-free contact plug 审中-公开
标题翻译：无空隙接触插头
公开(公告)号：US20080254617A1
公开(公告)日：2008-10-16
申请号：US11733519
申请日：2007-04-10
申请人： Olubunmi O. Adetutu , Elsie D. Banks , Jeffrey W. Thomas
发明人： Olubunmi O. Adetutu , Elsie D. Banks , Jeffrey W. Thomas
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer (30), a titanium nitride barrier layer (40), and a tungsten seed layer (50) in a contact opening (24). The contact hole (24) is then filled up from a bottom surface of the contact opening by electroplating a copper layer (60) so that no voids are formed in the contact opening (24). Any excess metal is removed with a CMP process to form the contact plugs (70), where the CMP process may also used to thin or remove one or more of the contact/seed/barrier layers (30, 40, 50).
摘要翻译：用于形成接触插塞的半导体器件制造方法包括在接触开口（24）中顺序地沉积钛或钽接触层（30），氮化钛阻挡层（40）和钨籽晶层（50）。接触孔（24）然后通过电镀铜层（60）从接触开口的底表面填充，使得在接触开口（24）中不形成空隙。通过CMP工艺去除任何多余的金属以形成接触塞（70），其中CMP工艺也可以用于稀释或去除一个或多个接触/种子/阻挡层（30,40,50）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式