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21. 发明申请

US20160140039A1 PROVIDING MULTIPLE MEMORY MODES FOR A PROCESSOR INCLUDING INTERNAL MEMORY 有权
标题翻译：为包括内部存储器的处理器提供多个存储器模式
公开(公告)号：US20160140039A1
公开(公告)日：2016-05-19
申请号：US14541504
申请日：2014-11-14
申请人： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
发明人： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
IPC分类号： G06F12/08 , G11C14/00
CPC分类号： G06F12/0646 , G06F12/023 , G06F2212/283
摘要： In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：形成在管芯上的至少一个核以执行指令; 第一存储器控制器，与内置存储器接口; 第二存储器控制器，与平台存储器接口以耦合到处理器; 以及位于所述处理器的包装内的所述包装内存储器，其中所述包装内存储器将被识别为相对于所述至少一个核心比所述平台存储器更远的存储器。描述和要求保护其他实施例。

22. 发明申请

US20110067011A1 TRANSFORMATION OF SINGLE-THREADED CODE TO SPECULATIVE PRECOMPUTATION ENABLED CODE 审中-公开
标题翻译：将单线程代码转换为使用初始化的代码
公开(公告)号：US20110067011A1
公开(公告)日：2011-03-17
申请号：US12949630
申请日：2010-11-18
申请人： Hong Wang , Perry H. Wang , Ross David Weldon , Scott M. Ettinger , Hideki Saito , Milind B. Girkar , Steve Shih-wei Liao , Mohammad R. Haghighat , Xinmin Tian , John P. Shen , Oren Gershon
发明人： Hong Wang , Perry H. Wang , Ross David Weldon , Scott M. Ettinger , Hideki Saito , Milind B. Girkar , Steve Shih-wei Liao , Mohammad R. Haghighat , Xinmin Tian , John P. Shen , Oren Gershon
IPC分类号： G06F9/45
CPC分类号： G06F9/544 , G06F9/52
摘要： In one embodiment a thread management method identifies in a main program a set of instructions that can be dynamically activated as speculative precomputation threads. A wait/sleep operation is performed on the speculative precomputation threads between thread creation and activation, and progress of non-speculative threads is gauged through monitoring a set of global variables, allowing the speculative precomputation threads to determine its relative progress with respect to non-speculative threads.
摘要翻译：在一个实施例中，线程管理方法在主程序中标识可以被动态地激活为推测性预计算线程的一组指令。在线程创建和激活之间的推测预先计算线程上执行等待/休眠操作，并且通过监视一组全局变量来衡量非推测线程的进度，允许推测性预计算线程确定其相对于非线性的非计算线程的相对进度，投机线。

23. 发明授权

US07984431B2 Method and apparatus for exploiting thread-level parallelism 有权
标题翻译：利用线程级并行性的方法和装置
公开(公告)号：US07984431B2
公开(公告)日：2011-07-19
申请号：US11695012
申请日：2007-03-31
申请人： Arun Kejariwal , Xinmin Tian , Wei Li , Milind B. Girkar
发明人： Arun Kejariwal , Xinmin Tian , Wei Li , Milind B. Girkar
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by overlapping; that is, all iterations must impose a partial execution order. According to one embodiment, the inventive subject matter may be used to transform the dependence structure of a given loop with recurrences for maximal degree of thread-level parallelism (TLP), where the threads can be mapped on to either different logical processors (in a hyperthreaded processor) or can be mapped onto different physical cores (or processors) in a multi-core processor.
摘要翻译：根据一个示例性实施例，这里公开了在多核计算机体系结构上使用部分递归松弛来并行化DOACROSS循环。通过一个示例定义，DOACROSS可以是允许通过重叠执行连续迭代的循环; 也就是说，所有迭代必须强制执行部分执行顺序。根据一个实施例，本发明的主题可以用于以线程级并行度（TLP）的最大程度的递归来转换给定循环的依赖结构，其中线程可以被映射到不同的逻辑处理器（在超线程处理器）或可以映射到多核处理器中的不同物理核心（或处理器）上。

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