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21. 发明申请

US20120098042A1 SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
标题翻译：具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US20120098042A1
公开(公告)日：2012-04-26
申请号：US12911186
申请日：2010-10-25
申请人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/04
CPC分类号： H01L21/2257 , H01L21/28512 , H01L21/28518 , H01L29/665 , H01L29/66643
摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.
摘要翻译：公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。具体地说，形成具有p-n结的半导体层。在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

22. 发明授权

US08030154B1 Method for forming a protection layer over metal semiconductor contact and structure formed thereon 失效
标题翻译：用于在金属半导体接触和其上形成的结构上形成保护层的方法
公开(公告)号：US08030154B1
公开(公告)日：2011-10-04
申请号：US12849223
申请日：2010-08-03
申请人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
发明人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.
摘要翻译：在一个实施例中，提供了一种形成半导体器件的方法，其包括在半导体衬底上提供栅极结构。侧壁间隔件可以与栅极结构相邻地形成。可以在栅极结构的上表面和与栅极结构相邻的半导体衬底的暴露表面上形成金属半导体合金。将金属半导体合金的上表面转化为含氧保护层。使用对含氧保护层具有选择性的蚀刻来去除侧壁间隔物。应变诱导层形成在栅极结构和半导体表面上，其中应变诱导层的至少一部分与栅极结构的侧壁表面直接接触。在另一个实施方案中，金属半导体合金的含氧保护层通过两阶段退火工艺提供。

23. 发明授权

US08592308B2 Silicided device with shallow impurity regions at interface between silicide and stressed liner 失效
标题翻译：在硅化物和应力衬里之间的界面具有浅杂质区的硅化器件
公开(公告)号：US08592308B2
公开(公告)日：2013-11-26
申请号：US13186587
申请日：2011-07-20
申请人： Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
发明人： Javier Ayala , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L29/78
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/28052 , H01L21/823418 , H01L29/665
摘要： A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
摘要翻译：形成半导体器件的方法包括形成场效应晶体管（FET）的硅化物接触区域; 在硅化物接触区的顶表面中形成浅杂质区; 以及在所述FET上形成应力衬垫，使得所述浅杂质区位于所述硅化物接触区域和所述受应力衬垫之间的界面处，其中所述浅杂质区域包括一种或多种杂质，并且被配置为阻止所述硅的扩散硅化物接触区域，并防止硅化物接触区域的形态退化。

24. 发明授权

US08482076B2 Method and structure for differential silicide and recessed or raised source/drain to improve field effect transistor 有权
标题翻译：差分硅化物和凹陷或凸起源极/漏极的方法和结构，以改善场效应晶体管
公开(公告)号：US08482076B2
公开(公告)日：2013-07-09
申请号：US12560585
申请日：2009-09-16
申请人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
发明人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/28 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
摘要翻译：一种方法形成集成电路结构。该方法在第一类场效应晶体管上形成保护层，并从第二种场效应晶体管上方去除应力衬垫。然后，该方法从第二类型场效应晶体管的源极区和漏极区去除第一类型的硅化物层，但是将第一类型硅化物层的至少一部分留在第二类型场效应晶体管的栅极导体上。该方法在栅极导体和第二类场效应晶体管的源极和漏极区域上形成第二类型的硅化物层。所形成的第二类硅化物层与第一型硅化物层不同。例如，第一型硅化物层和第二类型硅化物层可以包括不同的材料，不同的厚度，不同的晶体取向和/或不同的化学相等。

25. 发明授权

US07759208B1 Low temperature ion implantation for improved silicide contacts 失效
标题翻译：低温离子注入用于改善硅化物接触
公开(公告)号：US07759208B1
公开(公告)日：2010-07-20
申请号：US12412406
申请日：2009-03-27
申请人： Asa Frye , Christian Lavoie , Ahmet S. Ozcan , Donald R. Wall
发明人： Asa Frye , Christian Lavoie , Ahmet S. Ozcan , Donald R. Wall
IPC分类号： H01L21/36
CPC分类号： H01L21/265 , H01L21/28518 , H01L29/665 , H01L29/78
摘要： Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.
摘要翻译：本发明的实施方案提供了一种将基材冷却至低于10℃的温度，然后在基材的温度低于10℃时将离子注入基底中的方法。植入会导致基底的第一深度的损伤以在基底中产生非晶化区域。该方法在衬底上形成金属层并加热衬底，直到金属与衬底反应并在衬底的非晶化区域内形成硅化物区域。硅化物区域的深度至少与第一深度一样深。

26. 发明授权

US08927422B2 Raised silicide contact 有权
标题翻译：引起硅化物接触
公开(公告)号：US08927422B2
公开(公告)日：2015-01-06
申请号：US13525401
申请日：2012-06-18
申请人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
发明人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
IPC分类号： H01L21/44 , H01L21/31 , H01L21/285 , H01L29/66 , H01L21/02 , H01L21/8238
CPC分类号： H01L21/28518 , H01L21/02063 , H01L21/28525 , H01L21/76814 , H01L21/823814 , H01L23/485 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
摘要翻译：一种用于形成高硅化物接触的方法，包括使用气体簇注入技术在合同沟槽的底部沉积硅层，所述气体簇注入技术加速硅原子簇，导致它们穿过硅化物顶表面上的表面氧化物，宽度的硅化物和接触沟槽基本相等; 将包含硅层的硅化物在惰性气氛中加热至约300℃至约950℃的温度，使来自硅层的硅与部分形成在含硅衬底中的剩余硅化物反应; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。

27. 发明授权

US08895379B2 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same 有权
标题翻译：集成电路具有具有降低的硅化物接触电阻的升高的源极漏极器件和用于制造它们的方法
公开(公告)号：US08895379B2
公开(公告)日：2014-11-25
申请号：US13344806
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

28. 发明授权

US08889537B2 Implantless dopant segregation for silicide contacts 有权
标题翻译：用于硅化物接触的无植入物掺杂剂分离
公开(公告)号：US08889537B2
公开(公告)日：2014-11-18
申请号：US12833272
申请日：2010-07-09
申请人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
发明人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
IPC分类号： H01L21/28 , H01L21/285 , H01L29/45
CPC分类号： H01L21/28512 , H01L21/28518 , H01L29/456
摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
摘要翻译：在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

29. 发明授权

US08859316B2 Schottky junction si nanowire field-effect bio-sensor/molecule detector 有权
标题翻译：肖特基结si纳米线场效应生物传感器/分子检测器
公开(公告)号：US08859316B2
公开(公告)日：2014-10-14
申请号：US12825527
申请日：2010-06-29
申请人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
发明人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/00 , H01L29/06 , G01N27/414
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译：肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

30. 发明授权

US08741753B2 Use of band edge gate metals as source drain contacts 有权
标题翻译：使用带边栅极金属作为源极漏极触点
公开(公告)号：US08741753B2
公开(公告)日：2014-06-03
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20 , H01L21/3205 , H01L21/00
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

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