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    • 21. 发明授权
    • Method for forming a DRAM capacitor
    • 用于形成DRAM电容器的方法
    • US6162680A
    • 2000-12-19
    • US317132
    • 1999-05-24
    • Chine-Gie Lou
    • Chine-Gie Lou
    • H01L21/02H01L21/8242H01L21/20
    • H01L28/87H01L27/10852H01L28/55H01L28/91
    • The method for forming a capacitor in the present invention includes the steps as follows. At first, a multi-layer structure is formed on a semiconductor substrate, and the multi-layer structure is provided to have etching selectivity in etching neighboring layers in the multi-layer structure. A top dielectric layer is then formed on the multi-layer structure. A first opening is defined in the top dielectric layer, and a second opening is defined in the multi-layer structure under the first opening. Next, a wet etch is performed through the second opening to form at least two lateral openings in the multi-layer structure. Following the wet etch, a first conductive layer is formed conformably on the top dielectric layer, on sidewalls of the first opening and the second opening, and filled within the at least two lateral openings. A filling layer is then formed on the substrate, and the filling layer and the first conductive layer on the top dielectric layer are removed. The remained filling layer, the top dielectric layer, and the multi-layer structure are removed to leave a first electrode on the substrate. Finally, an inter-electrode dielectric layer is formed on the first electrode and a second conductive layer is formed on the inter-electrode dielectric layer to finish the formation of a capacitor.
    • 在本发明中形成电容器的方法包括以下步骤。 首先,在半导体衬底上形成多层结构,并且提供多层结构以在多层结构中蚀刻相邻层的蚀刻选择性。 然后在多层结构上形成顶部电介质层。 第一开口限定在顶部电介质层中,并且在第一开口下的多层结构中限定第二开口。 接下来,通过第二开口进行湿蚀刻以在多层结构中形成至少两个侧向开口。 在湿蚀刻之后,第一导电层在第一开口和第二开口的侧壁上在顶部电介质层上顺应地形成,并且填充在至少两个侧向开口内。 然后在基板上形成填充层,并且去除顶部介电层上的填充层和第一导电层。 去除剩余的填充层,顶部电介质层和多层结构,以在衬底上留下第一电极。 最后,在第一电极上形成电极间电介质层,在电极间电介质层上形成第二导电层,结束电容器的形成。
    • 22. 发明授权
    • Method for making fin-trench structured DRAM capacitor
    • 制造鳍沟结构DRAM电容的方法
    • US6100129A
    • 2000-08-08
    • US189353
    • 1998-11-09
    • Yeur-Luen TuChine-Gie Lou
    • Yeur-Luen TuChine-Gie Lou
    • H01L21/02H01L21/8242H01L21/8244
    • H01L28/82H01L27/10852H01L28/87H01L28/91
    • A method for manufacturing a fin-trench capacitor is disclosed. The method comprises the steps of: forming a plurality of alternating oxide and nitride layers including a top oxide layer, wherein said nitride layers are sandwiched between said oxide layers; forming a storage node contact opening in said plurality of alternating oxide and nitride layers, stopping at said landing pad; removing a portion of said nitride layers along sidewalls of said contract opening; forming a polysilicon layer over said top oxide layer and conformally along said sidewalls of said contact opening; depositing a photoresist layer into said contact opening; removing a portion of said polysilicon layer on top of said top oxide layer; forming a dielectric layer over said top oxide layer and conformally on top of said polysilicon layer along said sidewalls of said contact opening; forming a top conductive layer over said dielectric layer and in said contact opening.
    • 公开了一种用于制造鳍状沟槽电容器的方法。 该方法包括以下步骤:形成包括顶部氧化物层的多个交替的氧化物和氮化物层,其中所述氮化物层夹在所述氧化物层之间; 在所述多个交替的氧化物和氮化物层中形成存储节点接触开口,在所述着陆焊盘处停止; 沿着所述合约开口的侧壁去除所述氮化物层的一部分; 在所述顶部氧化物层上形成多晶硅层,并沿着所述接触开口的所述侧壁共形地形成多晶硅层; 将光致抗蚀剂层沉积到所述接触开口中; 在所述顶部氧化物层的顶部上去除所述多晶硅层的一部分; 在所述顶部氧化物层上形成电介质层,并沿着所述接触开口的所述侧壁保形地位于所述多晶硅层的顶部上; 在所述介​​电层上和所述接触开口中形成顶部导电层。
    • 23. 发明授权
    • Method for forming a DRAM capacitor
    • 用于形成DRAM电容器的方法
    • US06074913A
    • 2000-06-13
    • US108901
    • 1998-07-01
    • Chine-Gie LouYeur-Luen Tu
    • Chine-Gie LouYeur-Luen Tu
    • H01L21/02H01L21/285H01L21/8242
    • H01L28/92H01L21/28568H01L27/10852H01L28/84
    • A method for manufacturing a metal-insulator-metal capacitor on a substrate is disclosed. The method comprises the steps of: forming a first dielectric layer onto said substrate; patterning and etching said first dielectric layer to form a contact opening; forming a first metal layer onto said first dielectric layer and into said contact opening; forming a barrier layer onto said first metal layer; forming a second dielectric layer onto said barrier layer; forming a discrete HSG layer onto said second dielectric layer; etching said second dielectric layer by using said HSG layer as a mask; stripping said HSG layer; etching said barrier layer and said first metal layer by using a remaining portion of said second dielectric layer as a mask; stripping said remaining portion of said second dielectric layer; patterning and etching a remaining portion of said barrier layer and a remaining portion of said first metal layer; forming a third dielectric layer over said barrier layer, said first metal layer and said first dielectric layer; and forming a second metal layer over said third dielectric layer.
    • 公开了一种在衬底上制造金属 - 绝缘体 - 金属电容器的方法。 该方法包括以下步骤:在所述衬底上形成第一电介质层; 图案化和蚀刻所述第一介电层以形成接触开口; 在所述第一介电层上形成第一金属层并进入所述接触开口; 在所述第一金属层上形成势垒层; 在所述阻挡层上形成第二电介质层; 在所述第二介电层上形成离散的HSG层; 通过使用所述HSG层作为掩模蚀刻所述第二介质层; 剥离HSG层; 通过使用所述第二介电层的剩余部分作为掩模蚀刻所述阻挡层和所述第一金属层; 剥离所述第二电介质层的剩余部分; 图案化和蚀刻所述阻挡层的剩余部分和所述第一金属层的剩余部分; 在所述阻挡层上形成第三电介质层,所述第一金属层和所述第一介电层; 以及在所述第三介电层上形成第二金属层。
    • 24. 发明授权
    • Selective W CVD plug process with a RTA self-aligned W-silicide barrier
layer
    • 具有RTA自对准W硅化物阻挡层的选择性W CVD插塞工艺
    • US6048794A
    • 2000-04-11
    • US954048
    • 1997-10-20
    • Hsueh-Chung ChenChine-Gie Lou
    • Hsueh-Chung ChenChine-Gie Lou
    • H01L21/285H01L21/768H01L21/44
    • H01L21/28518H01L21/76879
    • The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.
    • 本发明提供一种使用具有自对准的W-硅化物阻挡层34的选择性W CVD工艺制造与衬底接触的钨(W)插头36的方法。该方法包括以下步骤:将第一绝缘层20形成在 硅半导体衬底10; 在第一绝缘层20中形成暴露基板表面的第一(接触)开口24; 在暴露的衬底表面上选择性地生长薄的第一钨层30; 从薄的第一钨层30快速热退火形成薄的第一硅化钨层34; 在基本上填充第一开口36的第一薄钨硅酸盐层34上选择性地沉积钨塞36,从而形成W插头接触。 RTA / W硅化物层34降低了接触电阻,增加了粘附性,并且有助于W插塞36的选择性沉积。
    • 25. 发明授权
    • Automatically adjustable wafer probe card
    • 自动调节晶圆探针卡
    • US06856156B2
    • 2005-02-15
    • US10400758
    • 2003-03-26
    • Sheng-Hui LiangChine-Gie Lou
    • Sheng-Hui LiangChine-Gie Lou
    • G01R1/073G01R31/02
    • G01R1/07392
    • An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.
    • 一种用于测试在晶圆上制造的集成电路的可自动调节的晶圆探针卡。 晶片探针卡包括具有移位块的俯仰移位组件,该移位块包括备用针块和相邻的功能性针座。 多个探针可以在移位块上线性调节,根据被探针接触的集成电路上的接触焊盘的数量,可将选定数量的探针从储备针头块移动到功能性针头块 的测试过程中的晶圆探针卡。 可以通过沿着功能性针块将探针定位在彼此间隔的选定间距来实现探针之间的间距或间距。
    • 26. 发明授权
    • Method for forming salicide process
    • 形成自杀过程的方法
    • US06784098B1
    • 2004-08-31
    • US09845477
    • 2001-04-30
    • Chine-Gie Lou
    • Chine-Gie Lou
    • H01L214763
    • H01L29/6659H01L21/28052H01L21/28518H01L29/66545H01L29/6656
    • A new method is provided for forming salicided surfaces to a FET device. Gate electrodes are formed including Ti/TiN salicided contact surface regions thereto. A thin layer of silicon oxide and a thick layer of photoresist are deposited. The layer of photoresist is polished, stopping on a top layer of BN of the gate electrode. The exposed layer of BN is removed. A thick layer of Ti/TiN is next deposited and annealed, forming TiSix after which unreacted Ti/TiN is removed. A high temperature anneal is applied to reduce the sheet resistance of the layer of TiSix. As an alternate approach to the above cited sequence the layer of photoresist can be replaced with a layer of boro-phosphate-silicate-glass (BPSG), the layer of BN can be replaced with a layer of silicon nitride.
    • 提供了一种用于在FET器件中形成水银表面的新方法。 栅电极被形成为包括Ti / TiN的水银接触表面区域。 沉积薄层的氧化硅和厚的光致抗蚀剂层。 光致抗蚀剂层被抛光,停留在栅电极的BN的顶层上。 去除BN的暴露层。 接着沉积并退火Ti / TiN厚层,形成TiSix,然后除去未反应的Ti / TiN。 施加高温退火以降低TiSix层的薄层电阻。 作为上述序列的替代方法,光致抗蚀剂层可以用硼磷酸盐 - 硅酸盐玻璃(BPSG)层替代,BN层可以用氮化硅层代替。
    • 27. 发明授权
    • Low thermal budget method for forming MIM capacitor
    • 用于形成MIM电容器的低热预算法
    • US06451650B1
    • 2002-09-17
    • US09838519
    • 2001-04-20
    • Chine-Gie Lou
    • Chine-Gie Lou
    • H01L218242
    • H01L28/88H01L28/92
    • The next generation of DRAM capacitors will require base electrodes having large effective surface areas and, additionally, will need to be manufactured with the expenditure of minimal energy (low thermal budgets). This is achieved in the present invention by use of a material other than silicon for the base electrode so that silicon HSGs (hemispherical grains) can be used as masks. By using disilane, rather than the more conventional silane, the HSGs can be formed at significantly lower temperatures and their size and mean separation can be well controlled. With the HSGs in place, the base electrode is etched so that its surface area is significantly increased. After removal of the HSGs, a suitable dielectric layer may be laid down, including high K materials such as barium strontium titanate, and the capacitor completed with the deposition of a suitable top electrode.
    • 下一代DRAM电容器将需要具有大的有效表面积的基极,并且另外需要以最小能量(低热预算)的支出来制造。 这在本发明中通过使用除了硅之外的材料作为基底电极来实现,使得可以使用硅HSG(半球形晶粒)作为掩模。 通过使用乙硅烷,而不是更常规的硅烷,HSG可以在显着更低的温度下形成,并且可以很好地控制其尺寸和平均分离。 使用HSG就可以对基极进行蚀刻,使其表面积显着增加。 在去除HSG之后,可以放置合适的电介质层,包括高K材料如钛酸锶钡,并且电容器通过沉积合适的顶部电极而完成。
    • 28. 发明授权
    • Method for forming a via and interconnect in dual damascene
    • 在双镶嵌中形成通孔和互连的方法
    • US06440847B1
    • 2002-08-27
    • US09845479
    • 2001-04-30
    • Chine-Gie Lou
    • Chine-Gie Lou
    • H01L214763
    • H01L21/7681H01L21/76804H01L2221/1063
    • A first low-k layer is formed over a structure having an exposed active device. A patterned first nitride layer having an opening therethrough aligned over a portion of the active device is formed. Nitride spacers are formed over the side walls of the opening. A second low-k layer is formed over the patterned first nitride layer, filling the patterned first nitride layer opening. The second low-k layer and the first low-k layer through the opening reduced by the nitride spacers are patterned to expose a portion of the active device to form a preliminary dual damascene. The nitride spacers and the first nitride layer exposed by the preliminary dual damascene opening are removed to form a final upper horizontal interconnect opening having substantially 90° edges. The first and second low-k layers are then reflowed to round the substantially 90° edges of the first and second low-k layer.
    • 在具有暴露的有源器件的结构上形成第一低k层。 形成具有在有源器件的一部分上对准的开口的图案化的第一氮化物层。 在开口的侧壁上形成氮化物间隔物。 在图案化的第一氮化物层上形成第二低k层,填充图案化的第一氮化物层开口。 通过由氮化物间隔物减少的开口的第二低k层和第一低k层被图案化以暴露有源器件的一部分以形成初步双镶嵌。 去除由初步双镶嵌开口暴露的氮化物间隔物和第一氮化物层,以形成具有大致90°边缘的最终的上部水平互连开口。 然后,第一和第二低k层被回流以围绕第一和第二低k层的大致90°的边缘。
    • 29. 发明授权
    • Method for forming a shallow trench isolation
    • 形成浅沟槽隔离的方法
    • US06403486B1
    • 2002-06-11
    • US09845482
    • 2001-04-30
    • Chine-Gie Lou
    • Chine-Gie Lou
    • H01L21302
    • H01L21/76224
    • A method is disclosed to form a shallow trench isolation (STI) without reverse short channel effect. This is accomplished by forming oxidized polysilicon spacers in the dielectric layers above the trench, while also employing a thermal oxide liner on the inside walls of the trench in the substrate. The polyoxide spacers and the thermal oxide liner together prevent the undercutting at the corners or shoulders of the trench, thereby avoiding the common problem of having reverse short channel effect.
    • 公开了形成没有反向短通道效应的浅沟槽隔离(STI)的方法。 这通过在沟槽上方的电介质层中形成氧化多晶硅间隔物,同时在衬底中的沟槽的内壁上采用热氧化物衬垫来实现。 多氧化物间隔物和热氧化物衬垫一起防止在沟槽的拐角或肩部处的底切,从而避免了具有反向短通道效应的常见问题。
    • 30. 发明授权
    • Dual damascene CMP process with BPSG reflowed contact hole
    • 双镶嵌CMP工艺与BPSG回流接触孔
    • US06239017B1
    • 2001-05-29
    • US09156357
    • 1998-09-18
    • Chine-Gie LouHsueh-Chung Chen
    • Chine-Gie LouHsueh-Chung Chen
    • H01L214763
    • H01L21/76828H01L21/31612H01L21/31625H01L21/76804H01L21/76807H01L2221/1036
    • An improved and new process for fabricating a planarized dual damascene contact hole and trench structure, wherein the contact holes have tapered sidewalls, has been developed. The dual damascene contact hole and trench are formed in a three layer insulator structure, in which the middle layer is a doped silicon oxide having a lower reflow temperature than the undoped silicon oxide layers forming the top and bottom layers. The contact holes are etched through the doped silicon oxide layer and the bottom undoped silicon oxide layer. The trenches are etched through the top undoped silicon oxide layer. After etching tapered sidewalls are formed at the contact holes by reflow of the doped silicon oxide through which the holes are etched.
    • 已经开发了一种用于制造平面化双镶嵌接触孔和沟槽结构的改进和新工艺,其中接触孔具有锥形侧壁。 双镶嵌接触孔和沟槽形成为三层绝缘体结构,其中中间层是具有比形成顶层和底层的未掺杂氧化硅层低的回流温度的掺杂氧化硅。 通过掺杂氧化硅层和底部未掺杂的氧化硅层蚀刻接触孔。 通过顶部未掺杂的氧化硅层蚀刻沟槽。 蚀刻之后,通过掺杂氧化硅的回流在接触孔处形成锥形侧壁,通过该掺杂氧化硅蚀刻孔。