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21. 发明申请

US20100062693A1 TWO STEP METHOD AND APPARATUS FOR POLISHING METAL AND OTHER FILMS IN SEMICONDUCTOR MANUFACTURING 审中-公开
标题翻译：用于在半导体制造中抛光金属和其他膜的两步法和装置
公开(公告)号：US20100062693A1
公开(公告)日：2010-03-11
申请号：US12205266
申请日：2008-09-05
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Ku-Feng Yang , Jung-Chih Hu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Ku-Feng Yang , Jung-Chih Hu
IPC分类号： B24C3/00
CPC分类号： H01L21/67219 , B24B37/04
摘要： A method and apparatus for removing a metal or conductive film from over a surface of a semiconductor wafer provides a two step process carried out within a single wafer processing apparatus. A first step is a wet chemical or mechanical removal process that removes an upper portion of the film at a high removal rate and is followed by a second step of a lower removal rate, the second step being CMP, chemical mechanical polishing.
摘要翻译：从半导体晶片表面上去除金属或导电膜的方法和装置提供了在单个晶片处理装置内执行的两步工艺。第一步是湿化学或机械去除工艺，其以高去除速率去除膜的上部，随后是较低去除速率的第二步骤，第二步是CMP，化学机械抛光。

22. 发明申请

US20080268614A1 Wafer Bonding 有权
标题翻译：晶圆贴合
公开(公告)号：US20080268614A1
公开(公告)日：2008-10-30
申请号：US11740178
申请日：2007-04-25
申请人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L21/30
CPC分类号： H01L21/2007
摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.
摘要翻译：提供一种用于提供堆叠晶片配置的方法。该方法包括将第一晶片接合到第二晶片。将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

23. 发明授权

US08500182B2 Vacuum wafer carriers for strengthening thin wafers 有权
标题翻译：用于加强薄晶片的真空晶片载体
公开(公告)号：US08500182B2
公开(公告)日：2013-08-06
申请号：US12818022
申请日：2010-06-17
申请人： Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： B25J15/00
CPC分类号： H01L21/67346 , H01L21/6838 , H01L21/68785
摘要： An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.
摘要翻译：用于支撑晶片的装置包括基座和气体穿透层。气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。气体通道被直接设置在气体穿透层上方的晶片密封。该装置还包括连接到气体通道的阀。

24. 发明授权

US08362593B2 Method for stacking semiconductor dies 有权
标题翻译：半导体晶片堆叠方法
公开(公告)号：US08362593B2
公开(公告)日：2013-01-29
申请号：US13168351
申请日：2011-06-24
申请人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L29/06
CPC分类号： H01L21/486 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/13009 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73203 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01019 , H01L2224/11
摘要： A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.
摘要翻译：公开了一种用于堆叠半导体管芯的系统和方法。优选实施例包括形成通过晶片的穿硅通孔，保护晶片的边缘边缘，然后去除未受保护的部分，使得边缘边缘的厚度大于薄的晶片。该厚度有助于脆弱的晶片在进一步的运输和工艺步骤中保持生存。然后优选在从晶片分离单个模具期间移除边缘。

25. 发明授权

US08119500B2 Wafer bonding 有权
标题翻译：晶圆接合
公开(公告)号：US08119500B2
公开(公告)日：2012-02-21
申请号：US11740178
申请日：2007-04-25
申请人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L21/30
CPC分类号： H01L21/2007
摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.
摘要翻译：提供了提供堆叠晶片配置的方法。该方法包括将第一晶片接合到第二晶片。将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

26. 发明授权

US08058150B2 Particle free wafer separation 有权
标题翻译：无颗粒晶圆分离
公开(公告)号：US08058150B2
公开(公告)日：2011-11-15
申请号：US12170494
申请日：2008-07-10
申请人： Weng-Jin Wu , Ku-Feng Yang , Jung-Chih Hu , Wen-Chih Chiou , Chen-Hua Yu
发明人： Weng-Jin Wu , Ku-Feng Yang , Jung-Chih Hu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer.
摘要翻译：公开了一种用于分离半导体晶片的方法。优选的实施方案包括在晶片的一侧上形成擦洗线，并用临时填充材料填充擦洗线。然后通过从磨擦线从晶片的相对侧移除材料来使晶片变薄，从而在相对侧上暴露临时填充材料。然后移除临时填充材料，并且将单个模具从晶片上移除。

27. 发明授权

US07466028B1 Semiconductor contact structure 有权
标题翻译：半导体接触结构
公开(公告)号：US07466028B1
公开(公告)日：2008-12-16
申请号：US11873037
申请日：2007-10-16
申请人： Chen-Hua Yu , Wen-Chih Chiou , Hung-Jung Tu , Weng-Jin Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Hung-Jung Tu , Weng-Jin Wu
IPC分类号： H01L27/10 , H01L29/73 , H01L29/74 , H01L23/02 , H01L23/04 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/0688 , H01L23/481 , H01L25/0657 , H01L2223/6616 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.
摘要翻译：提供了一种用于三维集成电路的半导体器件结构。半导体器件结构包括：具有第一表面和第二表面的衬底; 通孔，其限定在所述基板中并且从所述第一表面延伸到所述第二表面; 以及在所述第一表面上接触所述通孔的第一多个接触结构。平行于第一表面的第一多个接触结构中的每一个的横截面具有第一侧和第二侧，并且第一侧和第二侧的长边与短边的比例大于约2 ：1。

28. 发明授权

US08629565B2 Thin wafer protection device 有权
标题翻译：薄晶片保护装置
公开(公告)号：US08629565B2
公开(公告)日：2014-01-14
申请号：US13419078
申请日：2012-03-13
申请人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Tsung-Ding Wang
发明人： Ku-Feng Yang , Weng-Jin Wu , Wen-Chih Chiou , Tsung-Ding Wang
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/16 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68368 , H01L2221/68381 , H01L2224/16145 , H01L2224/32145 , H01L2224/80006 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/81005 , H01L2224/81801 , H01L2224/83005 , H01L2224/8385 , H01L2224/94 , H01L2224/95001 , H01L2225/06541 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1434 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/83
摘要： A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.
摘要翻译：薄晶片保护装置包括具有多个半导体芯片的晶片。晶片具有第一侧和相对的第二侧。多个管芯在晶片的第一侧上方，多个管芯中的至少一个与多个半导体芯片中的至少一个接合。晶片载体在晶片的第二面之上。封装层在晶片的第一侧和多个管芯之上，并且封装层具有平坦的顶表面。粘合带在封装层的平坦顶表面之上。

29. 发明授权

US07951647B2 Performing die-to-wafer stacking by filling gaps between dies 有权
标题翻译：通过填充管芯之间的间隙进行晶片间的堆叠
公开(公告)号：US07951647B2
公开(公告)日：2011-05-31
申请号：US12140695
申请日：2008-06-17
申请人： Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Ming-Chung Sung
发明人： Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Ming-Chung Sung
IPC分类号： H01L21/76
CPC分类号： H01L24/94 , H01L21/561 , H01L23/481 , H01L25/50 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/81 , H01L2224/83 , H01L2224/48
摘要： An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.
摘要翻译：集成电路结构包括底部半导体芯片; 顶部芯片结合到底部半导体芯片上; 围绕底模和底部半导体芯片的保护材料; 以及在顶模和保护材料上方的平面介电层。保护材料具有与顶模的顶表面平齐的顶表面。

30. 发明授权

US07972969B2 Method and apparatus for thinning a substrate 有权
标题翻译：减薄基板的方法和装置
公开(公告)号：US07972969B2
公开(公告)日：2011-07-05
申请号：US12043714
申请日：2008-03-06
申请人： Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Kewei Zuo
发明人： Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Kewei Zuo
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/67253 , H01L21/30604 , H01L21/6708 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for controlling substrate thickness. At least one etchant is dispensed from at least one dispenser to a plurality of different locations on a surface of a spinning substrate to perform etching. A thickness of the spinning substrate is monitored at the plurality of locations, so that the thickness of the substrate is monitored at each individual location while dispensing the etchant at that location. A respective amount of etching performed at each individual location is controlled, based on the respective monitored thickness at that location.
摘要翻译：提供了一种控制基板厚度的方法。至少一种蚀刻剂从纺丝衬底的表面从至少一个分配器分配到多个不同位置以进行蚀刻。在多个位置监测纺丝衬底的厚度，从而在每个单独位置监测衬底的厚度，同时在该位置分配蚀刻剂。基于在该位置处的相应监视的厚度来控制在每个单独位置执行的相应的蚀刻量。

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