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21. 发明授权

US06992669B2 Integrated graphics processing unit with antialiasing 有权
公开(公告)号：US06992669B2
公开(公告)日：2006-01-31
申请号：US10198707
申请日：2002-07-17
申请人： John S. Montrym , Douglas A. Voorhies , Steven E. Molnar
发明人： John S. Montrym , Douglas A. Voorhies , Steven E. Molnar
IPC分类号： G06T17/00
CPC分类号： G06T11/40 , G06T15/005 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the graphics data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data received from the lighting module. During use, an antialiasing feature is implemented on the single semiconductor platform to improve a quality of the graphics rendering.

22. 发明授权

US08704836B1 Distributing primitives to multiple rasterizers 有权
标题翻译：将原语分发到多个光栅化器
公开(公告)号：US08704836B1
公开(公告)日：2014-04-22
申请号：US12581700
申请日：2009-10-19
申请人： Johnny S. Rhoades , Steven E. Molnar , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
发明人： Johnny S. Rhoades , Steven E. Molnar , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
IPC分类号： G06F15/16
CPC分类号： G06T15/005 , G06T11/40 , G06T2210/12 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
摘要翻译：本发明的一个实施例提出了一种用于将原语并行分配到多个光栅化器的技术。多个独立的几何单元在不同的图形基元上同时执行几何处理。原始分配方案以每个时钟的多个基元的速率将原始图元从多个几何单元同时传送到多个光栅化器。多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

23. 发明授权

US08493395B2 Hardware override of application programming interface programmed state 有权
标题翻译：硬件覆盖应用程序编程接口编程状态
公开(公告)号：US08493395B2
公开(公告)日：2013-07-23
申请号：US13550468
申请日：2012-07-16
申请人： Jerome F. Duluk, Jr. , Henry P. Moreton , Steven E. Molnar , John S. Montrym
发明人： Jerome F. Duluk, Jr. , Henry P. Moreton , Steven E. Molnar , John S. Montrym
IPC分类号： G06F3/14 , G06F11/00 , G06F11/30 , G06F13/14 , G06F12/00 , G06T1/00
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译：使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。

24. 发明授权

US08059128B1 Apparatus and method for performing blit operations across parallel processors 有权
标题翻译：在并行处理器上执行blit操作的装置和方法
公开(公告)号：US08059128B1
公开(公告)日：2011-11-15
申请号：US11407464
申请日：2006-04-19
申请人： Justin S. Legakis , Mark J. French , Steven E. Molnar , Lukito Muliadi
发明人： Justin S. Legakis , Mark J. French , Steven E. Molnar , Lukito Muliadi
IPC分类号： G06F15/80 , G06F21/00
CPC分类号： G09G5/363 , G09G2352/00 , G09G2360/127
摘要： A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.
摘要翻译：在并行处理系统中执行blit操作的方法包括将blit操作划分成多个像素，以任何顺序执行与第一批次相关联的像素的读取，确认与第一批相关联的所有像素读取完成，以及以任何顺序执行与第一批相关联的像素的写入。第一批的像素和附加批次的像素被应用于并行处理器，其中并行处理器包括通过分布在并行处理器上的入口点和出口点定义的畜栏。

25. 发明申请

US20110090251A1 ALPHA-TO-COVERAGE VALUE DETERMINATION USING VIRTUAL SAMPLES 有权
标题翻译：使用虚拟样品的ALPHA到覆盖值确定
公开(公告)号：US20110090251A1
公开(公告)日：2011-04-21
申请号：US12904935
申请日：2010-10-14
申请人： Walter E. Donovan , Emmett M. Kilgariff , Steven E. Molnar , Christian Amsinck , Robert Ohannessian
发明人： Walter E. Donovan , Emmett M. Kilgariff , Steven E. Molnar , Christian Amsinck , Robert Ohannessian
IPC分类号： G09G5/00
CPC分类号： G06T15/503 , G06T15/005 , G09G5/363 , G09G5/393 , G09G2360/123
摘要： One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.
摘要翻译：本发明的一个实施例提出了一种将α值转换为像素覆盖掩码的技术。在每个像素内的多个“实”样本位置采样几何覆盖。为这些实际样本中的每一个计算颜色和深度值。片段α值用于确定实际样本和附加“虚拟”样本的alpha覆盖掩码，其中掩码位中设置的位数与alpha值成比例。与仅使用真实样本相比，alpha到覆盖模式使用虚拟样本来增加每个像素的透明度级别数。 alpha到覆盖模式可以与虚拟覆盖抗锯齿一起使用，以提供用于渲染抗锯齿图像的更高质量的透明度。

26. 发明申请

US20110072235A1 EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE 有权
标题翻译：高效的内存翻译器，具有可变尺寸的高速缓存线路覆盖
公开(公告)号：US20110072235A1
公开(公告)日：2011-03-24
申请号：US12851483
申请日：2010-08-05
申请人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
发明人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/401 , G06F2212/652 , G06F2212/684
摘要： One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.
摘要翻译：本发明的一个实施例阐述了一种使用具有可变地址范围覆盖的压缩TLB高速缓存行来支持高吞吐量虚拟到物理地址转换的系统和方法。 TLB缓存行覆盖的内存量取决于页面大小和页表项（PTE）压缩级别。当发生TLB未命中时，分配具有可能大于或小于实际返回的PTE数据的地址范围的假定地址范围的高速缓存行。后续请求命中一个填充待处理的缓存行排队等待填充完成。当填充完成时，缓存行的地址范围设置为返回的PTE数据的地址范围。排队的请求被重播，任何落在实际地址范围之外的任何地址将被重新发布，潜在地产生额外的未命中和填充。

27. 发明授权

US07868901B1 Method and system for reducing memory bandwidth requirements in an anti-aliasing operation 有权
标题翻译：在抗锯齿操作中减少内存带宽要求的方法和系统
公开(公告)号：US07868901B1
公开(公告)日：2011-01-11
申请号：US11557085
申请日：2006-11-06
申请人： John H. Edmondson , Steven E. Molnar , Bengt-Olaf Schneider , Gary C. King , Michael J. M. Toksvig , Peter B. Holmqvist , James M. O'Connor
发明人： John H. Edmondson , Steven E. Molnar , Bengt-Olaf Schneider , Gary C. King , Michael J. M. Toksvig , Peter B. Holmqvist , James M. O'Connor
IPC分类号： G09G5/00
CPC分类号： G06T11/40 , G09G5/363 , G09G2320/02 , G09G2360/18
摘要： Embodiments of the present invention sets forth a method and system for reducing memory bandwidth requirements for an anti-aliasing operation. The first virtual coverage information for a pixel involved in an anti-aliasing operation is maintained in memory. If a certain operating condition of the anti-aliasing operation deterministically implies the second virtual coverage information for this pixel, the second virtual coverage information, as opposed to the first virtual coverage information, is used in the anti-aliasing operation. In such situations, since the virtual coverage information is implied, it does not have to be accessed from memory, thereby improving overall system performance.
摘要翻译：本发明的实施例提出了一种用于减少抗混叠操作的存储器带宽要求的方法和系统。涉及抗混叠操作的像素的第一虚拟覆盖信息被保持在存储器中。如果抗混叠操作的某个操作条件确定地意味着该像素的第二虚拟覆盖信息，则与抗第一虚拟覆盖信息相反的第二虚拟覆盖信息被用于抗锯齿操作。在这种情况下，由于隐含虚拟覆盖信息，因此不必从存储器访问，从而提高系统的整体性能。

28. 发明授权

US07859541B2 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation 有权
标题翻译：用于在图形系统中使用页表条目以提供用于地址转换的存储格式信息的装置，系统和方法
公开(公告)号：US07859541B2
公开(公告)日：2010-12-28
申请号：US12479571
申请日：2009-06-05
申请人： John S. Montrym , David B. Glasco , Steven E. Molnar
发明人： John S. Montrym , David B. Glasco , Steven E. Molnar
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
摘要翻译：图形系统利用页表条目来提供用于存储图形数据的存储格式的信息。页表条目又可用于地址转换。存储格式信息的示例性种类包括压缩模式，用于存储瓦片中的Z数据的打包模式或瓦片中的颜色数据，以及用于在分区存储器中的分区之间分配瓦片数据的模式。

29. 发明授权

US07804499B1 Variable performance rasterization with constant effort 有权
标题翻译：可变性能光栅化，不断努力
公开(公告)号：US07804499B1
公开(公告)日：2010-09-28
申请号：US11467665
申请日：2006-08-28
申请人： Steven E. Molnar , Franklin C. Crow , Blaise A. Vignon
发明人： Steven E. Molnar , Franklin C. Crow , Blaise A. Vignon
IPC分类号： G06T15/30
CPC分类号： G06T15/405 , G06T11/40 , G06T15/005
摘要： The current invention involves new systems and methods for providing variable rasterization performance suited to the size and shape of the primitives being rendered. Portions of pixel tiles that are fully covered by a graphics primitive are encoded and processed by the system as rectangles, rather than expanding to explicit samples. This accelerates the rendering of large primitives without increasing the computation resources used for rasterization. In some embodiments, these fully-covered regions can be rendered compressed without ever expanding into samples.
摘要翻译：本发明涉及用于提供适于正在渲染的图元的尺寸和形状的可变光栅化性能的新系统和方法。由图形原语完全覆盖的像素块的部分由系统编码和处理为矩形，而不是扩展到显式样本。这样可以加快渲染大型图元而不增加用于光栅化的计算资源。在一些实施例中，这些完全覆盖的区域可以被压缩而不会扩展到样本中。

30. 发明授权

US07620798B1 Latency tolerant pipeline synchronization 有权
标题翻译：延迟容限管道同步
公开(公告)号：US07620798B1
公开(公告)日：2009-11-17
申请号：US11554511
申请日：2006-10-30
申请人： Mark J. French , Steven E. Molnar
发明人： Mark J. French , Steven E. Molnar
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the different transaction streams. Portions of the state configuration correspond to portions of the data. Execution of the transaction streams is synchronized to ensure that each portion of the data is processed using the state configuration that corresponds to that portion of the data. The synchronization mechanism may be used for multiple synchronizations and when the synchronization signals are pipelined to meet chip-level timing requirements.
摘要翻译：同步机制用于在处理事务流的多个执行流水线之间同步事件。在每个事务流中包括一组共同的状态配置，以控制分布在不同事务流之间的数据的处理。状态配置的部分对应于数据的部分。事务流的执行被同步，以确保使用对应于数据的该部分的状态配置来处理数据的每个部分。同步机制可以用于多个同步，并且当同步信号被流水线以满足芯片级定时要求时。

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