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21. 发明申请

US20130093064A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130093064A1
公开(公告)日：2013-04-18
申请号：US13271256
申请日：2011-10-12
申请人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
发明人： Chien-Liang Lin , Shao-Wei Wang , Yu-Ren Wang , Ying-Wei Yen
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L21/02181 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.
摘要翻译：半导体工艺包括以下步骤。提供基板。在基板上形成具有高介电常数的介电层，其中形成电介质层的步骤包括：（a）形成金属氧化物层; （b）对金属氧化物层进行退火处理; 并重复执行步骤（a）和（b）。另外，本发明还提供了由所述半导体工艺形成的半导体结构。

22. 发明申请

US20130001707A1 FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： MOS晶体管的制造方法，Fin场效应晶体管及其制造方法
公开(公告)号：US20130001707A1
公开(公告)日：2013-01-03
申请号：US13174711
申请日：2011-06-30
申请人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/02332 , H01L29/512 , H01L29/66795 , H01L29/785
摘要： A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
摘要翻译： MOS晶体管的制造方法包括以下步骤。提供基板。在基板上形成栅介电层。进行包含氮等离子体和氦气的氮化处理，以对栅介质层进行氮化。还提供了鳍状场效应晶体管及其制造方法。

23. 发明申请

US20120264284A1 MANUFACTURING METHOD FOR METAL GATE STRUCTURE 审中-公开
标题翻译：金属结构的制造方法
公开(公告)号：US20120264284A1
公开(公告)日：2012-10-18
申请号：US13086410
申请日：2011-04-14
申请人： Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang , Chien-Liang Lin
发明人： Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang , Chien-Liang Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds.
摘要翻译：金属栅极结构的制造方法包括提供其上形成有栅极沟槽的衬底，在栅极沟槽中形成功函数金属层，并对功函数金属层进行退火处理。退火过程在400℃和500℃之间的温度下进行，并且在20秒至约180秒的温度下进行。

24. 发明授权

US08614152B2 Gate structure and a method for forming the same 有权
标题翻译：栅结构及其形成方法
公开(公告)号：US08614152B2
公开(公告)日：2013-12-24
申请号：US13115186
申请日：2011-05-25
申请人： Chien-Liang Lin , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
发明人： Chien-Liang Lin , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
IPC分类号： H01L21/31
CPC分类号： H01L29/518 , B82Y40/00 , H01L21/28035 , H01L21/28176 , H01L21/28202 , H01L29/4925
摘要： A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.
摘要翻译：一种形成栅极结构的方法包括以下步骤。提供基板。在基板上形成氧化硅层。对氧化硅层施加去耦等离子体氮化处理以形成氮氧化硅层。在氮氧化硅层上形成第一多晶硅层。对具有第一多晶硅层的氧氮化硅层施加热处理。在热处理之后，在第一多晶硅层上形成第二多晶硅层。第一多晶硅层可以在热处理期间保护栅极介电层。栅极电介质层内的氮原子不会从栅介质层中流出。因此，可以避免排气现象，并且不能改变栅极电介质层的介电常数，从而增加栅极结构的可靠性。

25. 发明授权

US08501636B1 Method for fabricating silicon dioxide layer 有权
标题翻译：制造二氧化硅层的方法
公开(公告)号：US08501636B1
公开(公告)日：2013-08-06
申请号：US13556247
申请日：2012-07-24
申请人： Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Ying-Wei Yen , Kun-Yuan Lo , Chih-Wei Yang
发明人： Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Ying-Wei Yen , Kun-Yuan Lo , Chih-Wei Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02052 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.
摘要翻译：公开了制造二氧化硅层的方法。该方法包括以下步骤。首先，提供半导体衬底。接下来，用含有过氧化氢的溶液清洗半导体衬底，以在半导体衬底上形成化学氧化物层。然后，化学氧化物层在无氧气氛中加热，使得化学氧化物层形成致密层。然后，在氧气氛中加热半导体衬底，以在半导体衬底和致密层之间形成二氧化硅层。

26. 发明申请

US20120329285A1 GATE DIELECTRIC LAYER FORMING METHOD 审中-公开
标题翻译：门电介质层形成方法
公开(公告)号：US20120329285A1
公开(公告)日：2012-12-27
申请号：US13165870
申请日：2011-06-22
申请人： Shao-Wei WANG , Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang
发明人： Shao-Wei WANG , Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang
IPC分类号： H01L21/3105 , H01L21/318 , H01L21/316
CPC分类号： H01L21/02332 , H01L21/022 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.
摘要翻译：栅介质层形成方法应用于金属氧化物半导体场效应晶体管的制造工艺。栅介质层形成方法包括以下步骤。首先，提供基板。然后，在基板上形成中间层。然后，在中间层上形成高k电介质层。进行氮化处理以将高k电介质层转换成氮化的高k电介质层。进行第一次低温氮化退火处理以用第一气体处理氮化的高k电介质层。然后，进行第二次低温氮化退火处理，以用第二气体处理氮化的高k电介质层。

27. 发明申请

US20120309171A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120309171A1
公开(公告)日：2012-12-06
申请号：US13118473
申请日：2011-05-30
申请人： Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
发明人： Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底，其中衬底包括其上的栅极结构; 在所述衬底上形成膜叠层并覆盖所述栅极结构，其中所述膜堆叠至少包括氧化物层和氮化物层; 移除所述薄膜叠层的一部分以形成邻近所述栅极结构的两侧的凹槽和所述栅极结构侧壁上的一次性间隔物; 并用包含硅原子的材料填充凹部，以形成刻面材料层。

28. 发明申请

US20140073111A1 Method of Forming Isolation Structure 有权
标题翻译：形成隔离结构的方法
公开(公告)号：US20140073111A1
公开(公告)日：2014-03-13
申请号：US13607798
申请日：2012-09-09
申请人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
发明人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/02247 , H01L21/02252 , H01L21/3211 , H01L21/76237 , H01L29/7846
摘要： The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
摘要翻译：本发明提供一种形成隔离结构的方法。提供衬底，并且在衬底中形成沟槽。接下来，在沟槽的表面上形成半导体层。进行氮化，以在半导体层中形成氮化层。最后，将绝缘层填充到沟槽中。

29. 发明授权

US08940615B2 Method of forming isolation structure 有权
标题翻译：形成隔离结构的方法
公开(公告)号：US08940615B2
公开(公告)日：2015-01-27
申请号：US13607798
申请日：2012-09-09
申请人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
发明人： Te-Lin Sun , Chien-Liang Lin , Yu-Ren Wang
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76232 , H01L21/02247 , H01L21/02252 , H01L21/3211 , H01L21/76237 , H01L29/7846
摘要： The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
摘要翻译：本发明提供一种形成隔离结构的方法。提供衬底，并且在衬底中形成沟槽。接下来，在沟槽的表面上形成半导体层。进行氮化，以在半导体层中形成氮化层。最后，将绝缘层填充到沟槽中。

30. 发明申请

US20060172554A1 METHOD OF FORMING GATE DIELECTRIC LAYER 有权
标题翻译：形成栅介质层的方法
公开(公告)号：US20060172554A1
公开(公告)日：2006-08-03
申请号：US10906008
申请日：2005-01-31
申请人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
发明人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
IPC分类号： H01L21/00 , H01L21/31 , H01L21/469
CPC分类号： H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.
摘要翻译：描述了形成栅介质层的方法。在半导体衬底上形成氧化硅层。然后，使用包含惰性气体和气态氮的等离子体，依次对氧化硅层进行第一和第二氮掺杂工艺以形成栅极电介质层。第一氮掺杂过程在低功率，低压和高惰性气体与氮气比之下进行，与第二氮掺杂过程相比。第一氮掺杂过程的较深氮分布和第二氮掺杂过程的较浅氮分布的组合产生更平坦的总氮分布分布，从而可以减少来自电介质穿过栅介质层的漏电流。

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