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    • 21. 发明申请
    • Kunitz domain polypeptide Zkun10
    • Kunitz结构域多肽Zkun10
    • US20050176105A1
    • 2005-08-11
    • US11082148
    • 2005-03-16
    • Paul SheppardBrian Fox
    • Paul SheppardBrian Fox
    • A61K38/00C07K14/81C07H21/04C07K14/755C12N9/64C12P21/04
    • C07K14/8114A61K38/00
    • Proteinase inhibitors comprising a Kunitz domain are disclosed. The Kunitz domain comprises a motif of amino acid residues as shown in SEQ ID NO:4, and the sequence of the Kunitz domain is shown in residues 57 through 107 of SEQ ID NO:2. The polypeptide also includes an N-terminal collagen domain in which a von Willebrand domain resides, and is shown in SEQ ID NO: 5. Also disclosed are methods for making the proteinase inhibitors, and expression vectors and cultured cells that are useful within the methods. The proteinase inhibitors may be used as components of cell culture media, in protein purification, and as inhibitors of protease degradation of plasma proteins.
    • 公开了包含Kunitz结构域的蛋白酶抑制剂。 Kunitz结构域包含如SEQ ID NO:4所示的氨基酸残基的基序,Kunitz结构域的序列显示于SEQ ID NO:2的残基57至107中。 多肽还包括其中von Willebrand结构域所在的N-末端胶原结构域,并且显示于SEQ ID NO:5中。还公开了制备蛋白酶抑制剂的方法,以及在该方法中有用的表达载体和培养细胞 。 蛋白酶抑制剂可以用作细胞培养基的组分,蛋白质纯化,以及作为血浆蛋白质蛋白酶降解的抑制剂。
    • 25. 发明授权
    • Micro-granular delay testing of configurable ICs
    • 可配置IC的微粒延迟测试
    • US08072234B2
    • 2011-12-06
    • US12785484
    • 2010-05-23
    • Brian Fox
    • Brian Fox
    • H03K19/00
    • G01R31/3177G01R31/3016G01R31/31725G01R31/318516G01R31/318519H03K19/17764
    • A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.
    • 描述了用于测试集成电路(IC)中的一组电路的方法。 IC包括用于可配置地执行多个操作的多个可配置电路。 该方法将IC配置为以一组满足一组评估标准的测试路径在用户模式下运行。 每个测试路径包括用于可控地存储存储元件接收的信号的可控存储元件。 该方法在用户模式下操作IC。 该方法读取存储在存储元件中的值,以确定该组电路是否在指定的性能限制内运行。