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    • 22. 发明授权
    • Pulse width modulation with effective high duty resolution
    • 具有高占空比分辨率的脉宽调制
    • US09490792B2
    • 2016-11-08
    • US12703239
    • 2010-02-10
    • Bin Zhao
    • Bin Zhao
    • H03K7/08H04N9/31H05B33/08H02M1/084
    • H03K7/08H02M1/084H04N9/3123H05B33/0818H05B33/0845Y02B20/346
    • A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.
    • 脉冲宽度调制(PWM)信号发生器产生对于相应的周期窗口具有指定的有效PWM占空比分辨率的PWM信号。 PWM信号发生器接收表示要实现的占空比的N位值,并将值X和Y分别设置为N位值的M个最低有效位和N-M个最高有效位。 可以基于用于时间产生每个PWM周期的时钟信号的值N和最大可实施频率来确定值M. PWM信号发生器产生2M个PWM周期的周期窗口,周期窗口的每个PWM周期具有Y或Y + 1的占空比。 具有占空比Y + 1的周期窗口中的PWM周期的数量基于值X,并且具有特定占空比的PWM周期在周期窗口内是连续的。
    • 27. 发明授权
    • Peak detection with digital conversion
    • 峰值检测与数字转换
    • US08040079B2
    • 2011-10-18
    • US12424326
    • 2009-04-15
    • Bin Zhao
    • Bin Zhao
    • H05B37/02
    • G01R19/2506H05B33/0815H05B33/0827
    • A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.
    • 峰值检测/数字化电路包括多个电平检测单元,每个电平检测单元具有响应于比较器的输出的具有时钟输入的比较器和触发器。 对于检测周期,响应于检测周期的开始,每个电平检测单元将触发器的数据输出信号配置为第一数据状态。 此外,每个电平检测单元被配置为使得比较器能够分别响应于具有第一数据状态或第二数据状态的数据输出信号。 当在检测期间比较器被使能时,电平检测单元响应于比较器将输入信号与相应参考电压电平的比较来配置触发器的数据输出信号。 在检测周期结束时,电平检测单元的触发器的数据输出信号用于确定表示输入信号的峰值电压电平的数字值。
    • 28. 发明申请
    • PULSE WIDTH MODULATION WITH EFFECTIVE HIGH DUTY RESOLUTION
    • 具有有效高分辨率的脉冲宽度调制
    • US20110193648A1
    • 2011-08-11
    • US12703239
    • 2010-02-10
    • Bin Zhao
    • Bin Zhao
    • H03K7/08
    • H03K7/08H02M1/084H04N9/3123H05B33/0818H05B33/0845Y02B20/346
    • A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.
    • 脉冲宽度调制(PWM)信号发生器产生对于相应的周期窗口具有指定的有效PWM占空比分辨率的PWM信号。 PWM信号发生器接收表示要实现的占空比的N位值,并将值X和Y分别设置为N位值的M个最低有效位和N-M个最高有效位。 可以基于用于时间产生每个PWM周期的时钟信号的值N和最大可实施频率来确定值M. PWM信号发生器产生2M个PWM周期的周期窗口,周期窗口的每个PWM周期具有Y或Y + 1的占空比。 具有占空比Y + 1的周期窗口中的PWM周期的数量基于值X,并且具有特定占空比的PWM周期在周期窗口内是连续的。
    • 30. 发明申请
    • SERIAL CONFIGURATION FOR DYNAMIC POWER CONTROL IN LED DISPLAYS
    • LED显示屏动态功率控制串行配置
    • US20100201278A1
    • 2010-08-12
    • US12367672
    • 2009-02-09
    • Bin Zhao
    • Bin Zhao
    • H05B37/02
    • H05B33/0827H05B33/0815H05B33/0857
    • A power management technique in a light emitting diode (LED) system is disclosed. The LED system includes a plurality of LED driver connected in series, each LED driver configured to regulate the current flowing through a corresponding subset of a plurality of LED strings. Each LED driver determines the minimum tail voltage of the LED strings of the corresponding subset, compares the determined minimum tail voltage with an indicator of a minimum tail voltage of one or more other subsets provided from an upstream LED driver in the series, and then provides an indicator of the lower of the two tail voltages to the downstream LED driver. In this manner an indicator of the minimum tail voltage of the plurality of LED strings is cascaded through the series. A feedback controller monitors the minimum tail voltage represented by the cascaded indicator and accordingly adjusts an output voltage provided to the head ends of the plurality of LED strings.
    • 公开了一种发光二极管(LED)系统中的电源管理技术。 LED系统包括串联连接的多个LED驱动器,每个LED驱动器被配置为调节流过多个LED串的相应子集的电流。 每个LED驱动器确定相应子集的LED串的最小尾电压,将所确定的最小尾电压与从该系列中的上游LED驱动器提供的一个或多个其他子集的最小尾电压的指示器进行比较,然后提供 指示下游LED驱动器的两个尾部电压中较低的一个。 以这种方式,多个LED串的最小尾电压的指示器通过该系列级联。 反馈控制器监视由级联指示器表示的最小尾电压,并相应地调整提供给多个LED串的头端的输出电压。