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    • 21. 发明申请
    • High Speed Memory Module
    • 高速内存模块
    • US20100020584A1
    • 2010-01-28
    • US12505344
    • 2009-07-17
    • Chao Xu
    • Chao Xu
    • G11C5/06G11C7/00
    • G11C5/063G11C5/04H05K1/0237H05K1/14H05K2201/044H05K2201/09227H05K2201/10159
    • A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three positions for connecting memory modules. A plurality of memory chips may be mounted on the circuit board. The circuit board may include a plurality of D/Q traces to couple a corresponding plurality of D/Q signals from respective contacts to the plurality of memory chips or to one or more buffer chips that isolate the system memory bus from the memory chips. Each of the plurality of D/Q traces may have a predetermined trace impedance selected to provide a predetermined D/Q signal quality level when the memory module is installed in any of the three positions on the system memory bus and equivalent memory modules are installed in the other two positions.
    • 存储器模块可以包括可通过沿着电路板的一个边缘布置的多个触点连接到系统存储器总线的电路板,该系统存储器总线具有用于连接存储器模块的三个位置。 多个存储器芯片可以安装在电路板上。 电路板可以包括多个D / Q迹线,用于将来自相应触点的相应多个D / Q信号耦合到多个存储器芯片或将系统存储器总线与存储器芯片隔离的一个或多个缓冲器芯片。 当存储器模块安装在系统存储器总线上的三个位置中的任何位置中并且等效的存储器模块安装在多个D / Q迹线中时,每个D / Q迹线可以具有被选择用于提供预定的D / Q信号质量水平的预定迹线阻抗 另外两个职位。
    • 22. 发明授权
    • Amplitude and bandwidth pre-emphasis of a data signal
    • 数据信号的幅度和带宽预加重
    • US07327814B1
    • 2008-02-05
    • US11422252
    • 2006-06-05
    • Chao Xu
    • Chao Xu
    • H04B1/10
    • H04L25/03878
    • A data transmitter pre-emphasizes the amplitude and frequency bandwidth of a data signal. A data tap generator delays the data signal to generate multiple data tap signals, each of which is delayed by an integer multiple of a data period. A delay module further delays one of the data tap signals by a delay time that is less than the data period to generate a delayed data signal. The delay time of the delayed data signal determines a frequency bandwidth pre-emphasis for the data signal. A filter module multiplies the amplitudes of the data tap signals and the delayed data signal by coefficients to generate signal components of a pre-emphasized data signal. The coefficients of the filter module determine the amplitude pre-emphasis for the data signal. The filter module sums the signal components to generate the pre-emphasized data signal, which includes both the frequency bandwidth pre-emphasis and the amplitude pre-emphasis.
    • 数据发射机预先强调数据信号的幅度和频率带宽。 数据抽头发生器延迟数据信号以产生多个数据抽头信号,每个数据抽头信号被延迟数据周期的整数倍。 延迟模块进一步将数据抽头信号之一延迟小于数据周期的延迟时间以产生延迟的数据信号。 延迟数据信号的延迟时间决定数据信号的频带预加重。 滤波器模块将数据抽头信号和延迟的数据信号的幅度乘以系数以产生预加重数据信号的信号分量。 滤波器模块的系数确定数据信号的幅度预加重。 滤波器模块将信号分量相加以产生预加重数据信号,其包括频带预加重和幅度预加重两者。