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21. 发明授权

US07254049B2 Method of comparison between cache and data register for non-volatile memory 有权
公开(公告)号：US07254049B2
公开(公告)日：2007-08-07
申请号：US11580660
申请日：2006-10-13
申请人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop A. Nazarian
发明人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop A. Nazarian
IPC分类号： G11C15/00 , G11C7/10
CPC分类号： G11C7/22 , G06F12/0893 , G11C16/3436 , G11C2207/2245 , G11C2216/14
摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

22. 发明申请

US20060245272A1 Method of comparison between cache and data register for non-volatile memory 有权
公开(公告)号：US20060245272A1
公开(公告)日：2006-11-02
申请号：US11116842
申请日：2005-04-28
申请人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
发明人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
IPC分类号： G11C7/06
CPC分类号： G11C7/22 , G06F12/0893 , G11C16/3436 , G11C2207/2245 , G11C2216/14
摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

23. 发明申请

US20060245270A1 RANDOM CACHE READ 有权
标题翻译：随机缓存阅读
公开(公告)号：US20060245270A1
公开(公告)日：2006-11-02
申请号：US11115489
申请日：2005-04-27
申请人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
IPC分类号： G11C7/10
CPC分类号： G11C7/1042 , G11C7/1051 , G11C16/26 , G11C2207/2245
摘要： A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.
摘要翻译：描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间感测和数据I / O。

24. 发明授权

US07688630B2 Programming memory devices 失效
标题翻译：编程存储器件
公开(公告)号：US07688630B2
公开(公告)日：2010-03-30
申请号：US12370810
申请日：2009-02-13
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

25. 发明授权

US07336536B2 Handling defective memory blocks of NAND memory devices 有权
标题翻译：处理NAND存储器件的缺陷存储块
公开(公告)号：US07336536B2
公开(公告)日：2008-02-26
申请号：US10876878
申请日：2004-06-25
申请人： Benjamin Louie , Aaron Yip
发明人： Benjamin Louie , Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C29/832 , G11C16/04 , G11C16/0483 , G11C29/26 , G11C29/789 , G11C29/82 , G11C2029/4402
摘要： Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.
摘要翻译：提供了装置和方法。 NAND存储器件具有包括多个存储器块的存储器阵列和耦合到每个存储器块的易失性锁存器，用于当该存储器块是已知缺陷块时选择性地防止与其耦合的存储器块的测试。非易失性锁存器还可以耦合到每个存储器块，以在存储器装置的正常操作期间永久地防止当该存储器块是已知缺陷块时与其耦合的相应存储器块的存取。

26. 发明授权

US07274607B2 Bitline exclusion in verification operation 有权
标题翻译：验证操作中的位线排除
公开(公告)号：US07274607B2
公开(公告)日：2007-09-25
申请号：US11153188
申请日：2005-06-15
申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
发明人： Hendrik Hartono , Aaron Yip , Benjamin Louie
IPC分类号： G11C7/12
CPC分类号： G11C16/3454 , G11C29/83 , G11C29/832
摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
摘要翻译：用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作失败了

27. 发明授权

US08520436B2 Programming memory devices 失效
公开(公告)号：US08520436B2
公开(公告)日：2013-08-27
申请号：US13464531
申请日：2012-05-04
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

28. 发明授权

US07532524B2 Bitline exclusion in verification operation 有权
标题翻译：验证操作中的位线排除
公开(公告)号：US07532524B2
公开(公告)日：2009-05-12
申请号：US11842531
申请日：2007-08-21
申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
发明人： Hendrik Hartono , Aaron Yip , Benjamin Louie
IPC分类号： G11C7/00
CPC分类号： G11C16/3454 , G11C29/83 , G11C29/832
摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
摘要翻译：用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作失败了

29. 发明授权

US07505323B2 Programming memory devices 失效
标题翻译：编程存储器件
公开(公告)号：US07505323B2
公开(公告)日：2009-03-17
申请号：US12025815
申请日：2008-02-05
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

30. 发明申请

US20090043975A1 MEMORY DEVICE TRIMS 有权
标题翻译：存储设备TRIMS
公开(公告)号：US20090043975A1
公开(公告)日：2009-02-12
申请号：US12246606
申请日：2008-10-07
申请人： Benjamin Louie , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Aaron Yip , Jin-Man Han
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/028
摘要： Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.
摘要翻译：提供了方法和装置。存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。存储器件可以包括对应于参考调整电路的指数电路。索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

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