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    • 28. 发明申请
    • COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS
    • 处理器核心部分之间的通信
    • US20090319705A1
    • 2009-12-24
    • US12141725
    • 2008-06-18
    • Annie FoongBryan E. VealArun Raghunath
    • Annie FoongBryan E. VealArun Raghunath
    • G06F13/00
    • G06F15/16
    • In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    • 在一个实施例中,提供了一种方法,其可以包括提供由平台中的第一处理器核心分区独占且可相干访问的第一地址空间。 可以在该实施例中提供第二地址空间,其由平台中的第二处理器核心分区专门地和相干地访问。 同样在该实施例中,可以提供平台中的第三地址空间,其至少部分地由第一和第二处理器核分区可访问,并且可以允许至少在第一和第二处理器核分区之间进行通信 一个分组和与所述至少一个分组相关联的至少一个描述符。 至少一个描述符可以至少部分地指示第三地址空间中的一个或多个位置,以至少部分地存储至少一个分组。 当然,在不脱离本实施例的情况下,许多替代,修改和变化是可能的。