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    • 21. 发明授权
    • Screen compression
    • 屏幕压缩
    • US07965895B1
    • 2011-06-21
    • US11837336
    • 2007-08-10
    • John M. DanskinZiyad S. HakuraEdward L. RiegelsbergerJason M. MusicerStephen D. Lew
    • John M. DanskinZiyad S. HakuraEdward L. RiegelsbergerJason M. MusicerStephen D. Lew
    • G06K9/36G06K9/46
    • G09G5/397G09G5/393G09G2340/02G09G2340/12G09G2360/122H04N19/428H04N19/593
    • Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
    • 用于减少由图形处理器使用的存储器带宽的方法,电路和装置。 未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。 未压缩的瓦片被压缩并写回图形存储器。 在修改瓦片之前,再次需要一个瓦片时,从内存中读取压缩版本,解压缩并显示。 为了将压缩瓦片的不必要的写入数量减少到存储器,如果在一些刷新周期内保持静态,则瓦片仅写入存储器。 此外,为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器,编码器可以在写入多个瓦片之后被节流。 有效信息可以存储供CRTC使用。 如果更新瓦片,则更新有效性信息,使得无法从存储器读取无效的压缩数据并显示。
    • 24. 发明授权
    • Redundant circuit presents connections on specified I/O ports
    • 冗余电路在指定的I / O端口上显示连接
    • US07622947B1
    • 2009-11-24
    • US11549597
    • 2006-10-13
    • John M. Danskin
    • John M. Danskin
    • G06F17/50H03K19/173
    • G11C29/848
    • A method and apparatus for utilizing redundant circuitry on integrated circuits (ICs) that may increase manufacturing yields, while maintaining a predetermined set of interfaces for connection with external circuitry without drastically increasing die area and circuit complexity are provided. In this manner, even though an IC may have defects which would otherwise render it inoperable, embodiments of the present invention allow the defects to be circumscribed or avoided while still maintaining a predetermined set of interfaces, thus providing for an operational circuit. Various embodiments further provide a method for sorting or separating devices based on their level of functionality or performance, which in turn depends on their number of defects and the desired number of interfaces.
    • 提供了一种用于在集成电路(IC)上利用冗余电路的方法和装置,其可以增加制造产量,同时保持用于与外部电路连接的预定接口组,而不会显着增加管芯面积和电路复杂度。 以这种方式,即使IC可能具有否则将使其不可操作的缺陷,本发明的实施例允许限制或避免缺陷,同时仍然保持预定的一组接口,从而提供操作电路。 各种实施例还提供了一种用于根据其功能或性能的级别对设备进行分类或分离的方法,其依赖于它们的缺陷数量和期望数量的接口。
    • 25. 发明授权
    • Stippled lines using direct distance evaluation
    • 使用直接距离评估的条纹线
    • US07554546B1
    • 2009-06-30
    • US11735041
    • 2007-04-13
    • Franklin C. CrowDouglas A. VoorhiesJohn M. Danskin
    • Franklin C. CrowDouglas A. VoorhiesJohn M. Danskin
    • G06T11/20
    • G06T11/203
    • Stippled lines are drawn by evaluating a distance function for a set of points within the area of a stippled line. The distance function gives a distance value proportional to the distance from a point to the end of the stippled line. Using the point's distance value, a pattern index value defines a correspondence between a point and at least one stipple pattern bit. The value of pattern bits are applied to the points on the stippled line, masking the points such that only a portion of the set of points are displayed or determining intensity values according to the position of the points within the stipple pattern. A distance function may be an edge equation associated with the line end or a segment of a polyline. The distance function can be evaluated for the set of points in any order, allowing portions of a stippled line to be drawn in parallel.
    • 通过评估点划线的区域内的一组点的距离函数来绘制条纹线。 距离函数给出与从刻点线到点的距离成比例的距离值。 使用点的距离值,模式索引值定义点与至少一个点模式位之间的对应关系。 图案位的值被应用于点画线上的点,掩蔽点,使得仅显示点集的一部分,或者根据点模式中的点的位置来确定强度值。 距离函数可以是与线端或折线的段相关联的边缘方程。 距离函数可以以任意顺序对点集合进行评估,允许点划线的部分并行绘制。
    • 27. 发明授权
    • A-Buffer compression for different compression formats
    • 用于不同压缩格式的A缓冲区压缩
    • US08654135B1
    • 2014-02-18
    • US12634460
    • 2009-12-09
    • John M. Danskin
    • John M. Danskin
    • G06T1/60G09G5/00
    • G06T1/60G06T9/00G06T11/40G06T15/503
    • One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer that supports multi-sample compression techniques. The A-Buffer is organized in stacks of uniformly-sized tiles, wherein the tile size is selected to facilitate compression techniques. Each stack represents the samples included in a group of pixels. Each tile within a stack represents the set of sample data at a specific per-sample rendering order index that are associated with the group of pixels represented by the stack. Advantageously, each tile includes tile compression bits that enable the tile to maintain data using existing compression formats. As the A-Buffer is created, a corresponding stack compression buffer is also created. For each stack, the stack compression buffer includes a bit that indicates whether all of the tiles in the stack are similarly compressed and, consequently, whether the GPU may operate on the stack at an efficient per pixel granularity.
    • 本发明的一个实施例提出了一种用于有效地创建和访问支持多样本压缩技术的A缓冲器的技术。 A缓冲器以均匀尺寸的瓦片的堆叠组织,其中选择瓦片尺寸以便于压缩技术。 每个堆栈表示包含在一组像素中的样本。 堆栈中的每个瓦片表示与由堆栈表示的像素组相关联的特定每样本渲染顺序索引处的采样数据集合。 有利地,每个瓦片包括瓦片压缩比特,使得瓦片能够使用现有的压缩格式来维护数据。 当创建A缓冲区时,也会创建相应的堆栈压缩缓冲区。 对于每个堆栈,堆栈压缩缓冲器包括指示堆栈中的所有瓦片是否被类似地压缩的位,并且因此,GPU是否可以以每像素粒度有效地在堆栈上操作。
    • 28. 发明授权
    • System and method for structuring an A-buffer to support multi-sample anti-aliasing
    • 用于构造A缓冲区以支持多样本抗锯齿的系统和方法
    • US08130223B1
    • 2012-03-06
    • US12208204
    • 2008-09-10
    • John M. Danskin
    • John M. Danskin
    • G06T15/40
    • G06T15/503G06T1/60G06T11/40
    • One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer that supports multi-sample compression techniques. The A-Buffer is organized in stacks of uniformly-sized tiles, wherein the tile size is selected to facilitate compression techniques. Each stack represents the samples included in a group of pixels. Each tile within a stack represents the set of sample data at a specific per-sample rendering order index that are associated with the group of pixels represented by the stack. Advantageously, each tile includes tile compression bits that enable the tile to maintain data using existing compression formats. As the A-Buffer is created, a corresponding stack compression buffer is also created. For each stack, the stack compression buffer includes a bit that indicates whether all of the tiles in the stack are similarly compressed and, consequently, whether the GPU may operate on the stack at an efficient per pixel granularity.
    • 本发明的一个实施例提出了一种用于有效地创建和访问支持多样本压缩技术的A缓冲器的技术。 A缓冲器以均匀尺寸的瓦片的堆叠组织,其中选择瓦片尺寸以便于压缩技术。 每个堆栈表示包含在一组像素中的样本。 堆栈中的每个瓦片表示与由堆栈表示的像素组相关联的特定每样本渲染顺序索引处的采样数据集合。 有利地,每个瓦片包括瓦片压缩比特,使得瓦片能够使用现有的压缩格式来维护数据。 当创建A缓冲区时,也会创建相应的堆栈压缩缓冲区。 对于每个堆栈,堆栈压缩缓冲器包括指示堆栈中的所有瓦片是否被类似地压缩的位,并且因此,GPU是否可以以每像素粒度有效地在堆栈上操作。
    • 29. 发明授权
    • System and method for structuring an A-buffer
    • US08026912B1
    • 2011-09-27
    • US11950352
    • 2007-12-04
    • John M. Danskin
    • John M. Danskin
    • G06T15/00
    • G06T15/005G06T11/40
    • One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer with a GPU. The A-Buffer is organized in arrays of uniformly-sized tiles. Each array represents a group of pixels, and each tile within an array includes the set of fragments at a specific depth complexity that are associated with the pixels in the pixel group represented by the array. The size of the tiles may be selected to be the minimum necessary for efficient memory access. The GPU determines the number of tiles in each array by calculating the maximum of the depth complexity associated with the pixels in the pixel group represented by the array and creates a corresponding prefix sum image to allow the GPU to efficiently locate the array associated with a given pixel group in the A-Buffer for addressing purposes. Advantageously, structuring the A-Buffer by both pixel proximity and depth complexity improves memory locality, thereby improving the overall rendering performance of the graphics pipeline.