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21. 发明申请

US20120105095A1 SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE 审中-公开
标题翻译：硅绝缘体（SOI）体接触通孔结构
公开(公告)号：US20120105095A1
公开(公告)日：2012-05-03
申请号：US12938440
申请日：2010-11-03
申请人： Andres Bryant , Edward J. Nowak , Robert R. Robison
发明人： Andres Bryant , Edward J. Nowak , Robert R. Robison
IPC分类号： G01R31/26
CPC分类号： H01L22/32 , G01R31/2621 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L27/1203 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.
摘要翻译：提供了一种用于测试浮体场效应晶体管（FET）的电路及相关方法。本发明的实施例包括可以以浮体模式或身体接触模式操作的接触体FET结构的电路和通道FET。接触体FET结构的主体连接到通道FET的漏极。可以将电压施加到通道FET，以允许或限制通过通道FET的电流，以在身体接触模式或浮体模式中操作接触体FET结构。数据可以在每种模式下进行比较，并提取浮体电压。

22. 发明授权

US08119474B2 High performance capacitors in planar back gates CMOS 有权
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US08119474B2
公开(公告)日：2012-02-21
申请号：US12688243
申请日：2010-01-15
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

23. 发明申请

US20110254059A1 STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US20110254059A1
公开(公告)日：2011-10-20
申请号：US13167303
申请日：2011-06-23
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L29/808 , H01L21/337 , B82Y99/00
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

24. 发明授权

US08034699B2 Isolation with offset deep well implants 有权
标题翻译：隔离与偏移深井植入物
公开(公告)号：US08034699B2
公开(公告)日：2011-10-11
申请号：US12464206
申请日：2009-05-12
申请人： James W. Adkisson , Andres Bryant , Mark D. Jaffe , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , Mark D. Jaffe , Alain Loiseau
IPC分类号： H01L21/425
CPC分类号： H01L29/1083 , H01L21/26513 , H01L21/823892
摘要： A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.
摘要翻译：一种方法是将杂质掺入晶体管的阱区。该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。去除第一个掩模，并在衬底上制备第二个掩模。该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。在衬底上制备第三个掩模。第三掩模具有比第一掩模和第二掩模中的开口小的开口。通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

25. 发明申请

US20110133280A1 DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS 失效
标题翻译：不同厚度的氧化硅纳米线场效应晶体管
公开(公告)号：US20110133280A1
公开(公告)日：2011-06-09
申请号：US12631148
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Andres Bryant , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Andres Bryant , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336 , H01L29/78
CPC分类号： H01L29/78696 , H01L29/42392
摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.
摘要翻译：产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。第一栅极氧化物比第二栅极氧化物厚。该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和第一线和第二线内的漏极区。

26. 发明申请

US20110101449A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20110101449A1
公开(公告)日：2011-05-05
申请号：US12985060
申请日：2011-01-05
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

27. 发明申请

US20110068399A1 INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE 有权
标题翻译：具有串联场效应晶体管和集成电压均衡的集成电路装置及其形成方法
公开(公告)号：US20110068399A1
公开(公告)日：2011-03-24
申请号：US12563195
申请日：2009-09-21
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/786 , H01L29/78 , H01L21/336
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译：公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接。集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

28. 发明授权

US07902000B2 MugFET with stub source and drain regions 有权
标题翻译： MugFET具有短路源极和漏极区域
公开(公告)号：US07902000B2
公开(公告)日：2011-03-08
申请号：US12132865
申请日：2008-06-04
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/72
CPC分类号： H01L29/785 , H01L29/66803
摘要： The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer.
摘要翻译：本发明提供一种半导体器件，其包括在衬底的表面上方的至少一个半导体鳍结构; 所述半导体鳍结构包括第一导电类型的沟道和第二导电类型的源极/漏极区，所述源/漏区存在于所述半导体鳍结构的每个端部处; 靠近半导体鳍片结构的栅极结构，邻接栅极结构的每个侧壁的电介质间隔物，其中翅片结构的每个端部从侧壁延伸小于约含有Si的鳍结构的长度的尺寸的电介质间隔物; 以及到半导体鳍片结构的每一端的半导体区域，其中半导体鳍片结构的每个端部的半导体区域通过电介质间隔物与栅极结构分离。

29. 发明授权

US07847320B2 Dense chevron non-planar field effect transistors and method 有权
标题翻译：密集V形非平面场效应晶体管及方法
公开(公告)号：US07847320B2
公开(公告)日：2010-12-07
申请号：US11939574
申请日：2007-11-14
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/80
CPC分类号： H01L27/0207 , H01L21/823412 , H01L29/785
摘要： Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.
摘要翻译：公开了半导体结构的实施例以及形成半导体结构的方法，其同时使器件密度最大化并避免接触栅极间距和鳍片间距失配，当在衬底上的有限区域内形成多个平行的有角度的鳍片然后穿过多个平行门（例如，在堆叠，人字形配置的CMOS设备的情况下）。这是通过使用而不是最小光刻鳍间距来实现的，而是通过使用根据预先选择的接触栅间距，预选翅片角和预选择的周期性图案计算的鳍间距来实现在有限的区域内相对于门定位翅片。因此，所公开的结构和方法允许将具有给定区域中的多个堆叠的平面FET的半导体产品设计布局转换成具有多个，堆叠的，人造V形的非平面FET的半导体产品设计布局区。

30. 发明申请

US20100301419A1 INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS ANDAN UNDERLYING FLOATING WELL SECTION 有权
标题翻译：集成电路设备，具有深层隔离隔离区域，用于所有内部和内部隔离以及与共享设备扩展区域之间的连接的共享接触，并且基于浮动井段
公开(公告)号：US20100301419A1
公开(公告)日：2010-12-02
申请号：US12473324
申请日：2009-05-28
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/088 , H01L29/772 , H01L21/335 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section.
摘要翻译：公开了改进的集成电路器件结构（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）的实施例，以及形成使用DTI区域的结构的方法从而提供了一种低成本的隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。此外，由于用于井内隔离的DTI区域有效地创建了一些浮动阱区段，其必须各自连接到电源电压（例如Vdd）以防止阈值电压（Vt）变化，所公开的集成电路器件还包括与相邻设备的扩散区域和下面的浮动井段之间的连接处共享接触。这种共享联系消除了如果每个浮动井段需要离散的电源电压接触将导致的成本和面积罚款。

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