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21. 发明申请

US20100049995A1 Enhanced Thermal Management for Improved Module Reliability 失效
标题翻译：增强热管理，提高模块可靠性
公开(公告)号：US20100049995A1
公开(公告)日：2010-02-25
申请号：US12194620
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcolm S. Ware , Roger D. Weekly
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.
摘要翻译：提供了数据处理系统中组件分层的缓解效应。从数据处理系统中的一个或多个传感器接收信号。确定信号是否指示已经达到或超过多个阈值中的一个阈值。响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。

22. 发明授权

US08645640B2 Method and apparatus for supporting memory usage throttling 失效
标题翻译：支持内存使用限制的方法和装置
公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。

23. 发明授权

US08214663B2 Using power proxies combined with on-chip actuators to meet a defined power target 有权
标题翻译：使用与片上执行器相结合的电源代理来满足定义的功率目标
公开(公告)号：US08214663B2
公开(公告)日：2012-07-03
申请号：US12424158
申请日：2009-04-15
申请人： Michael S. Floyd , Karthick Rajamani , Malcolm S. Ware
发明人： Michael S. Floyd , Karthick Rajamani , Malcolm S. Ware
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F1/3203
摘要： A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value.
摘要翻译：提供了一种机构，用于使用与片上致动器组合的功率代理单元，以满足识别数据处理系统的组件的目标功耗的定义的功率目标值。数据处理系统中的功率管理器针对所定义的功率目标值识别代理功率阈值，识别组件的最大功率使用量，以及标识组件的当前功率使用估计值的功率使用估计值。功率管理器响应于功率使用估计值大于功率代理阈值，向与组件相关联的功率代理单元中的一个或多个片上致动器发送一组信号。一个或多个片上致动器调整与组件相关联的一组操作参数，以便满足所定义的功率目标值。

24. 发明申请

US20100268974A1 Using Power Proxies Combined with On-Chip Actuators to Meet a Defined Power Target 有权
标题翻译：使用电源代理与片上执行器相结合来实现定义的电源目标
公开(公告)号：US20100268974A1
公开(公告)日：2010-10-21
申请号：US12424158
申请日：2009-04-15
申请人： Michael S. Floyd , Karthick Rajamani , Malcolm S. Ware
发明人： Michael S. Floyd , Karthick Rajamani , Malcolm S. Ware
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value.
摘要翻译：提供了一种机构，用于使用与片上致动器组合的功率代理单元，以满足识别数据处理系统的组件的目标功耗的定义的功率目标值。数据处理系统中的功率管理器针对所定义的功率目标值识别代理功率阈值，识别组件的最大功率使用量，以及标识组件的当前功率使用估计值的功率使用估计值。功率管理器响应于功率使用估计值大于功率代理阈值，向与组件相关联的功率代理单元中的一个或多个片上致动器发送一组信号。一个或多个片上致动器调整与组件相关联的一组操作参数，以便满足所定义的功率目标值。

25. 发明授权

US08650367B2 Method and apparatus for supporting memory usage throttling 失效
公开(公告)号：US08650367B2
公开(公告)日：2014-02-11
申请号：US13585268
申请日：2012-08-14
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.

26. 发明授权

US07917328B2 Tracking thermal mini-cycle stress 失效
标题翻译：跟踪热微循环应力
公开(公告)号：US07917328B2
公开(公告)日：2011-03-29
申请号：US12194606
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
IPC分类号： G06F19/00
CPC分类号： G06F11/3058
摘要： Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.
摘要翻译：提供了组装过程中组装体验的温度偏移。确定组件是否已经超出预定寿命目标的使用。响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。将累积的绩效值与累积压力的绩效预算进行比较。响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

27. 发明申请

US20100049466A1 Tracking Thermal Mini-Cycle Stress 失效
标题翻译：跟踪热微循环应力
公开(公告)号：US20100049466A1
公开(公告)日：2010-02-25
申请号：US12194606
申请日：2008-08-20
申请人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
发明人： Jon A. Casey , Michael S. Floyd , Soraya Ghiasi , Kenneth C. Marston , Jennifer V. Muncy , Malcom S. Ware , Roger D. Weekly
IPC分类号： G06F17/00 , G08B1/08
CPC分类号： G06F11/3058
摘要： Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.
摘要翻译：提供了组装过程中组装体验的温度偏移。确定组件是否已经超出预定寿命目标的使用。响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。将累积的绩效值与累积压力的绩效预算进行比较。响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

28. 发明申请

US20120079500A1 PROCESSOR USAGE ACCOUNTING USING WORK-RATE MEASUREMENTS 审中-公开
标题翻译：处理者使用工资率计量的会计
公开(公告)号：US20120079500A1
公开(公告)日：2012-03-29
申请号：US12893748
申请日：2010-09-29
申请人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal C. Swanberg
发明人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06Q30/06 , G06F11/3409 , G06F11/3438
摘要： Accounting charges are assigned to workloads by measuring a relative use of computing resources by the workloads, then scaling the results using determined work-rate for the corresponding workload. Usage metrics for the individual resources may be selectable for the resources being measured and the work-rates may be determined from an analytical model or from empirical model that determines work-rates from an indication of processor throughput. Under single workload conditions on a platform, or other suitable conditions, a workload type may be used to select the particular usage metrics applied for the various resources.
摘要翻译：通过测量工作负载的计算资源的相对使用，然后使用确定的相应工作负载工作率来缩放结果，将会计费用分配给工作负载。可以针对被测量的资源选择各个资源的使用度量，并且可以从分析模型或经验模型确定工作速率，该经验模型根据处理器吞吐量的指示来确定工作率。在平台上的单个工作负载条件或其他合适的条件下，可以使用工作负载类型来选择应用于各种资源的特定使用度量。

29. 发明申请

US20120005513A1 PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT 有权
标题翻译：通过电压调整对频率适配处理器进行性能控制
公开(公告)号：US20120005513A1
公开(公告)日：2012-01-05
申请号：US12827432
申请日：2010-06-30
申请人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
发明人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要翻译：包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。测量每个核心的性能并将其与目标性能进行比较。如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

30. 发明授权

US08527801B2 Performance control of frequency-adapting processors by voltage domain adjustment 有权
标题翻译：通过电压域调整对频率适配处理器进行性能控制
公开(公告)号：US08527801B2
公开(公告)日：2013-09-03
申请号：US12827432
申请日：2010-06-30
申请人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
发明人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要翻译：包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。测量每个核心的性能并将其与目标性能进行比较。如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

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